Vertical solid-state devices

ABSTRACT

As the pixel density of optoelectronic devices becomes higher, and the size of the optoelectronic devices becomes smaller, the problem of isolating the individual micro devices becomes more difficult. A method of fabricating an optoelectronic device, which includes an array of micro devices, comprises: forming a device layer structure including a monolithic active layer on a substrate; forming an array of first contacts on the device layer structure defining the array of micro devices; mounting the array of first contacts to a backplane comprising a driving circuit which controls the current flowing into the array of micro devices; removing the substrate; and forming an array of second contacts corresponding to the array of first contacts with a barrier between each second contact.

CROSS-REFERENCE TO RELATED APPLICATIONS

The application claims priority from U.S. Provisional PatentApplications Nos. 62/479,038, filed Mar. 30, 2017, and 62/533,394, filedJul. 17, 2017, and Canadian Patent Applications Nos. 2,986,412 filedNov. 14, 2017, and U.S. Pat. No. 2,987,165 filed Nov. 30, 2017, whichapplications are incorporated herein by reference in their entirety.

FIELD OF THE INVENTION

The present invention relates to vertical solid-state devices, lateralconduction manipulation of vertical solid-state devices, and methods ofmanufacture thereof. The present invention also relates to thefabrication of an integrated array of microdevices, defined by an arrayof contacts on a device substrate or a system substrate.

BACKGROUND

Integrating micro optoelectronic devices into a system substrate mayresult in high performance and high functionality systems. However, toreduce the cost and create higher pixel density devices, the size of theoptoelectronic devices should be reduced. Examples of optoelectronicdevices are sensors and light emitting devices, such as light emittingdiodes (LEDs). As the size of the optoelectronic devices is reduced;however, device performance may start to suffer. Some reasons forreduced performance include, higher leakage current due to defects,charge crowding at interfaces, imbalance charge, and unwantedrecombination, such as Auger and nonradiative recombination.

Light Emitting Diodes (LED) and LED arrays may be categorized as avertical solid-state device. The micro devices may be sensors, LightEmitting Diodes (LEDs) or any other solid devices grown, deposited ormonolithically fabricated on a substrate. The substrate may be thenative substrate of the device layers or a receiver substrate, to whichdevice layers or solid-state devices are transferred.

Various transferring and bonding methods may be used to transfer andbond device layers to the system substrate. In one example heat andpressure may be used to bond device layers to a system substrate. In avertical solid-state device, the current flow in the vertical directionpredominantly defines the functionality of the device.

Patterning LEDs into micro size devices to create an array of LEDs fordisplay applications comes with several issues, including materialutilization, limited PPI, and defect creation.

An object of the present invention is to overcome the shortcomings ofthe prior art by providing improved vertical solid-state devices.

This background information is provided for the purposes of making knowninformation believed by the applicant to be of possible relevance to thepresent invention. No admission is necessarily intended, nor should beconstrued, that any of the preceding information constitutes prior artagainst the present invention.

SUMMARY OF THE INVENTION

The present invention relates to an optoelectronic device, including anarray of micro devices, the optoelectronic device comprising:

a backplane comprising a driving circuit which controls the currentflowing into the micro devices and an array of pads connected to thedriving circuit;

an array of bottom contacts electrically connected to the drivingcircuit;

a device layer including a monolithic active layer;

an array of top contacts corresponding to the array of bottom contacts;

a common top electrode connected to all of the top contacts.

Another embodiment of the present invention relates to a method offabricating an optoelectronic device, including an array of microdevices, comprising:

forming a device layer on a substrate, the device layer including amonolithic active layer;

forming an array of first contacts on the device layer defining thearray of micro devices;

mounting the array of first contacts to a backplane comprising a drivingcircuit which controls the current flowing into the array of microdevices and an array of pads connected to the driving circuit;

removing the substrate; and

forming an array of second contacts corresponding to the array of firstcontacts.

BRIEF DESCRIPTION OF THE FIGURES

The foregoing and other advantages of the disclosure will becomeapparent upon reading the following detailed description and uponreference to the drawings.

FIG. 1A illustrates an optoelectronic device with at least twoterminals.

FIG. 1B illustrates an optoelectronic device with an MIS structure on atleast one side of the device.

FIG. 1C illustrates a top view of the optoelectronic device of FIG. 1Bwith MIS structures on the sides.

FIG. 2A illustrates an exemplary embodiment of a process for forming anMIS structure on an optoelectronic device prior to a transfer process.

FIG. 2B illustrates an exemplary embodiment of a process for forming anMIS structure on optoelectronic devices both prior to and after thetransfer process.

FIG. 2C illustrates an exemplary embodiment of a process for forming anMIS structure on an optoelectronic device after the transfer process.

FIG. 3 illustrates transferred micro devices with a negative slope on asystem substrate.

FIG. 4 illustrates a process flow chart of a wafer etching process formesa structure formation.

FIG. 5A illustrates transferred micro device with a positive slope onthe system substrate.

FIG. 5B illustrates the formation of different MIS structures ontransferred micro devices.

FIG. 5C illustrates the formation of a passivation or planarizationlayer, and the patterning the passivation or planarization layer forcreating opening for electrode connections.

FIG. 5D illustrates the deposition of electrodes on the micro devices.

FIG. 6A illustrates embodiments for the formation of different MISstructures on micro devices before the transfer process.

FIG. 6B illustrates micro devices with MIS structures transferred onto asystem substrate and different means for coupling the devices and MISstructures to electrodes or a circuit layer.

FIG. 6C illustrates micro devices with MIS structures transferred onto asystem substrate and different means for coupling the devices and MISstructures to electrodes or a circuit layer.

FIG. 7A illustrates another embodiment of the formation of different MISstructures on micro devices before the transfer process.

FIG. 7B illustrates micro devices with MIS structures transferred ontosystem substrate and different means for coupling the devices and MISstructures to electrodes or a circuit layer.

FIG. 8A illustrates a schematic of a vertical solid state micro deviceshowing the lateral current components and partially etched top layer.

FIG. 8B illustrates a side view of an array of micro devices including adevice layer with a partially etched top layer and top layer modulation.

FIG. 8C illustrates a side view of an array of micro devices including adevice layer with a top conductive modulation layer.

FIG. 8D illustrates a side view of an array of micro devices including adevice layer with nanowire structures.

FIG. 8E illustrates a cross section of an MIS structure surrounding acontact layer.

FIG. 8F illustrates a side view of an array of micro devise includingcontacts separated by dielectric or bonding layers.

FIG. 8G illustrates a side view of an array of micro devise includingcontacts separated by dielectric or bonding layers.

FIG. 9A illustrates a side view of a conventional Gallium nitride (GaN)LED device.

FIG. 9B illustrates a fabrication process of an LED display andintegration process of a device substrate with micro devices defined bytop contacts and bonding of the substrate to a system substrate.

FIG. 9C illustrates an LED wafer structure including an array of microdevices defined by the top contact.

FIG. 9D illustrates an LED wafer structure including an array of microdevices defined by the top contact and partially etched top conductivelayer.

FIG. 9E illustrates an LED wafer structure including an array of microdevices defined by the top contact and laser etching of the topconductive layer.

FIG. 9F illustrates a LED wafer including an array of micro devicesbonded to a backplane structure.

FIG. 9G illustrates a LED wafer including an array of micro devicesbonded to a backplane structure with a common top electrode.

FIG. 10A illustrates a LED wafer including an array of micro devicesbonded to a backplane structure with common transparent top electrode.

FIG. 10B illustrates an integrated LED wafer bonded to a systemsubstrate, and including an array of micro devices defined by topcontacts.

FIG. 10C illustrates a LED wafer with a buffer layer and metalliccontact vias.

FIG. 10D illustrates a LED wafer including an array of micro deviceswith a patterned top conductive layer.

FIG. 10E illustrates an integrated device substrate with micro devicesdefined by top contacts bonded to a system substrate.

FIG. 10F illustrates an integrated device substrate with micro devicesdefined by top contacts bonded to a system substrate and opticalelements formed between adjacent micro devices.

FIG. 10G illustrates a transferred LED wafer including an array of microdevices with patterned top conductive layer and light management scheme.

FIG. 10H illustrates a transferred LED wafer including an array of microdevices with patterned top conductive layer and light management scheme.

FIG. 10I illustrates a transferred LED wafer including an array of microdevices with patterned top conductive layer and light management scheme.

FIG. 10J illustrates a transferred LED wafer including an array of microdevices with patterned top conductive layer and light management scheme.

FIG. 10K illustrates a transferred LED wafer including an array of microdevices with patterned top conductive layer and light management scheme.

FIG. 10L illustrates stacked devices with isolation methods.

FIGS. 11A and 11B illustrate an integration process of a devicesubstrate and a system substrate.

FIGS. 12A to 12D illustrate an integration process of a device substrateand a system substrate.

FIGS. 13A and 13B illustrate an integration process of a devicesubstrate and a system substrate.

FIGS. 14A to 14C illustrate an integration process of a device substrateand a system substrate.

FIGS. 15A to 15C illustrate an integration process of a device substrateand a system substrate.

FIG. 16A illustrates a device with dielectric layer deposition on thewafer surface.

FIG. 16B illustrates a device with a dielectric layer etched to createan opening on the layer for subsequent wafer etching.

FIG. 16C illustrates mesa structures after a wafer substrate etchingstep.

FIG. 17 illustrates a process flow chart for formation of an MISstructure.

FIG. 18A illustrates a dielectric and metal layer deposited on a mesastructure to form an MIS structure.

FIG. 18B illustrates a wafer with a pattern formed usingphotolithography step.

FIG. 18C illustrates a wafer with a dielectric layer dry etched usingfluorine chemistry.

FIG. 18D illustrates a wafer with a second dielectric layer.

FIG. 18E illustrates a wafer with an ohmic contact.

FIG. 19 illustrates a schematic diagram of a floating gate for biasingthe walls of a semiconductor device.

FIG. 20 illustrates a semiconductor device including a floating gate forbiasing the walls of the semiconductor device.

FIG. 21 illustrates an exemplary flow chart of developing a floatinggate.

FIG. 22 illustrates a semiconductor device and a method of charging thefloating gate.

FIG. 23 illustrates another exemplary structure of a floating gate forbiasing the walls of a semiconductor device.

FIG. 24 illustrates another exemplary embodiment for biasing the wallsof a semiconductor device.

FIG. 25A illustrates a side view of another embodiment of an MISstructure.

FIG. 25B illustrates a top view of the MIS structure of FIG. 25A.

FIG. 25C illustrates a top view of another embodiment of an MISstructure.

FIG. 25D illustrates a top view of another embodiment of an MISstructure.

FIG. 26 illustrates a side view of another embodiment of an MISstructure.

FIGS. 27A to 27C illustrate a fabrication process of an LED display andintegration process of a device substrate with micro devices defined bytop contacts and bonding of the substrate to a system substrate.

FIGS. 28A to 28D illustrate a fabrication process of an LED display andintegration process of a device substrate with micro devices defined bytop contacts and bonding of the substrate to a system substrate.

FIGS. 29A to 29D illustrate a fabrication process of an LED display andintegration process of a device substrate with micro devices defined bytop contacts and bonding of the substrate to a system substrate.

FIGS. 30A to 30B illustrate a fabrication process of an LED display andintegration process of a device substrate with micro devices defined bytop contacts and bonding of the substrate to a system substrate.

DETAILED DESCRIPTION OF THE INVENTION

While the present teachings are described in conjunction with variousembodiments and examples, it is not intended that the present teachingsbe limited to such embodiments. On the contrary, the present teachingsencompass various alternatives and equivalents, as will be appreciatedby those of skill in the art.

Unless defined otherwise, all technical and scientific terms used hereinhave the same meaning as commonly understood by one of ordinary skill inthe art to which this invention belongs.

As used in the specification and claims, the singular forms “a”, “an”and “the” include plural references unless the context clearly dictatesotherwise.

The term “comprising” as used herein will be understood to mean that thelist following is non-exhaustive and may or may not include any otheradditional suitable items, for example one or more further feature(s),component(s) and/or element(s) as appropriate.

The terms “device” and “micro device” and “optoelectronic device” areused herein interchangeably. It would be clear to one skill in the artthat the embodiments described here are independent of the device size.

The terms “donor substrate” and “temporal substrate” are used hereininterchangeably. However, it is clear to one skill in the art that theembodiments described herein are independent of the substrate.

The terms “system substrate” and “receiver substrate” are used hereininterchangeably. However, it is clear to one skill in the art that theembodiments described here are independent of substrate type.

The present disclosure relates to methods for lateral conductionmanipulation of vertical solid-state devices, particularlyoptoelectronic devices. More specifically, the present disclosurerelates to micro or nano-optoelectronic devices in which the performanceof the device is being affected by a reduction in size. Also describedis a method of creating an array of vertical devices by modifying thelateral conduction without isolating the active layers. Also disclosedis an array of LEDs using vertical conductivity engineering enablingcurrent transport in a horizontal direction and controlled to the pixelarea, so there is no need for patterning the LEDs.

Herein is also described a method of LED structure modification tosimplify the integration of monolithic LED devices with backplanecircuitry in an LED display while preserving device efficiency anduniformity. The present methods and resulting structures increase thenumber of LED devices fabricated within a limited wafer area and mayresult in lower fabrication cost, decrease in the number of fabricationsteps, and higher resolution and brightness for the LED displays. LEDdevices in a substrate may be bonded to an electronic backplane, whichdrives the devices or pixels in passive or active manner. Although thefollowing methods are explained with one type of LED device, they can beeasily used with other LED and non-led vertical devices, such as, forexample, sensors. LED devices in a substrate as herein described may bebonded to an electronic backplane which drives these devices (pixels) inpassive or active manner.

Also described herein is a method of improving the performance of anoptoelectronic device by manipulating the internal electrical field ofthe device. In particular, limiting the lateral current flow of verticalsolid-state devices may improve the performance of the devices. Inparticular, diverging current from the perimeter of a vertical devicemay be accomplished by modifying the lateral conduction. The resistanceof the conductive layers may be modified by oxidation, and the lateralresistance of the conductive layers may be modified by modifying thebias condition. A contact can also be used as a mask to modify thelateral resistance of the conductive layer. The present devices may alsohave conductive layers on the sides and functional layers in the middle.

Also provided is a method of pixelating a display device by defining thepixel pad connection in a backplane and attaching the LED device withvertical conduction modulation to the backplane. In one embodiment, thecurrent spreader may be removed, or its thickness may be reduced tomodulate the vertical conduction. In another embodiment, some of themicro device layers may be etched to create vertical conductionmodulation. A bonding element may be used to hold the device to thebackplane. Structures and methods are described for defining microdevices on a device layer by forming contact pads on the device layerbefore transferring the device layer to a receiver substrate. Alsodescribed are structures and methods to define the micro devices bycontact pads or bumps on the receiver substrate in an integratedmicro-device array system comprising a transferred monolithic array ofmicro devices and a system substrate.

Also described are methods of manipulating the top conductive layer of avertical device in which the functionality of the device predominantlyis defined by the vertical currents. In one embodiment the methodcomprises: top layer resistance engineering in which the lateralresistance of the top layer may be manipulated by changing the thicknessor specific resistivity of the top layer; full or partial etchingmodulation in which the top layer of the vertical device may bemodulated by any means of etching; and material conductivity modulationin which the resistance of the top layer may be modulated by variousmethods including but not limited to etching, counter doping, and laserablation. The contact pads on the top device layer may define the sizeof the individual microdevices. After transfer of micro devices, acommon electrode may be deposited on the transferred monolithic array ofmicrodevices to improve the conductivity. The common electrodes may beformed through vias in the top buffer or dielectric layers transferredor deposited on the monolithic array of micro devices. Also, the toplayer of the transferred monolithic array of micro devices may bemodulated by any means of removing. In this case, optical elements maybe formed in the removed regions of the modulated top layer.

Also described is a method of forming an array of micro devices on anintegrated structure in which the device layer, prepared according toaforementioned methods, is transferred to a receiving substrate whereinthe contact pads on the top of the receiving substrate may be bonded tothe device layer and the size of the individual microdevices may bedefined partially by the size of contact pads or bumps on the receiversubstrate. Spacers or banks may be formed around contact pads or bumpsto fully define the size of the micro devices. The spacers or banksaround contact pads or bumps may be adhesives to promote bonding thedevice layer to the receiver substrate. The top layer of the integratedmicrodevice array may be modulated by any means of removing. In oneembodiment, the optical elements may be formed in the removed regions ofthe modulated top layer.

In an embodiment, at least one metal-insulator-semiconductor (MIS)structure may be formed with one of the device faces as semiconductorlayer. The structure may be used to manipulate the device internalelectrical field to control the charge transition and accumulation. TheMIS structure may be formed prior to moving the device into the systemsubstrate, or after the device is formed into the system substrate. Theelectrode in MIS structure may be transparent to let the light passthrough, or the electrode may be reflective or opaque to control thedirection of the light. Preferably the device output comprises visiblelight for creating an array of pixels in a display. The electrode in theMIS structure may be shared with one of the devices functionalelectrode. The electrode in the MIS structure may also have a separatebias point. The input or output of the micro devices may be any form ofelectromagnetic wave. Non-limiting examples of the device are a lightemitting diode and a sensor. Structures and methods for improving microoptoelectronic devices are also described herein. The device performancemay be improved by means of manipulating the internal electric field. Inone case, the MIS structure is used to modulate the internal electricalfield.

In micro device system integration, devices may be fabricated in theirnative ambient conditions, and may be then transferred to a systemsubstrate. To pack more micro devices in a system substrate or reducethe cost of material, the size of micro devices may be as small aspossible. In one example, the micro devices may be 25 μm or smaller andin another example 5 μm or smaller. As the original devices and layerson the donor substrate are being patterned to a smaller area, theleakage and other effects increase reducing the performance of thedevices. Although, passivation may improve the performance to someextent, it cannot address other issues such as, non-radiativerecombination.

Various embodiments in accordance with the present structures andprocesses provided are described below in detail.

Vertical Devices with Metal-Insulator-Semiconductor (MIS) Structures

Described is the use of a metal-insulator-semiconductor (MIS) structureto modulate the internal electric field of a vertical device to reducethe unwanted effects caused by reduction in the size. In one embodiment,the structure is fully formed on the devices in the donor or temporalsubstrate substrates and moved to the system substrate afterward. Inanother case, the MIS structure is formed on the devices integrated onreceiver or system substrate. In another case, the MIS structure isformed partially on the devices prior to integration into the receiversubstrate and the MIS structure is completed after transferring thedevice into the receiver substrate.

The system substrate may be any substrate and may be rigid or flexible.The system substrate may be made of glass, silicon, plastics or anyother commonly used material. The system substrate may also have activeelectronic components, such as but not limited to transistors,resistors, capacitors or any other electronic component commonly used ina system substrate. In some cases, the system substrate may be asubstrate with electrical signal rows and columns. In one example thedevice substrate may be a sapphire substrate with LED layers grownmonolithically thereon, and the system substrate may be a backplane withcircuitry to derive micro-LED devices. As part of the vertical devices,metal-insulator-semiconductor (MIS) structures may be formed from alayer of metal, a layer of insulating material, and a layer ofsemiconductor material.

With reference to FIG. 1A, a micro device 100 includes two functionalcontacts A 102 and B 104. Biasing the micro device 100 causes a current106 to flow through the bulk of the micro device 100. In the case oflight emitting devices, the charges recombine in light emitting layer(s)and create photons. In the case of sensing devices, the externalstimulation, e.g. light, chemical, Tera Hz, X-ray, etc., modulates thecurrent. However, the non-idealities may affect the efficiency of themicro device 100 in both cases. One example is the leakage current 108mainly caused by the defects in the side walls. Other non-idealities maybe non-radiative recombination, e.g. Auger recombination, chargecrowding, charge imbalance, etc. These issues become more dominate asthe size of the device is reduced.

With reference to FIG. 1B, the micro device 100 further includes ametal-insulator-semiconductor (MIS) structure 110 to modulate theinternal field and reduces some of the aforementioned issues. At leastone MIS structure 110 is formed on one of the faces of the micro device100. The MIS structure 110 is biased through an electrode 112. If theMIS structure 110 is formed on more than one surface of the micro device100, they may be a continuous structure or comprise a separate MISstructure 110. The electrodes 112 may be connected to provide the samebias for all faces or the electrodes may be independent providingdifferent biases for different MIS structure 110 and different faces.

In an exemplary embodiment illustrated in FIG. 1C, the MIS structure 110surrounds the micro device 100 in one continuous form on or around aplurality of faces of the micro device 100. Applying bias to the MISstructure 110 may reduce the leakage current 108 and/or avoid bandbending under high current density to avoid non-radiative recombinationand/or assists one of the charge to enhance the charge balance and avoidcurrent crowding. The biasing conditions may be chosen to fix thedominant issue. For example, in the case of a red light emitting diode(LED), leakage current is the major source of efficiency loss atmoderate to low current densities. In this case, the biasing conditionmay block/reduce the leakage current resulting in a significantefficiency boost. In another case, such as a green LED, Augerrecombination may be the main issue. The biasing condition may beadjusted to reduce this type of recombination. It is noted that one biascondition may eliminate/reduce more than other bias conditions and LEDtypes. Dynamic adjust of the biasing condition may also be provided forbetter performance. For example, in lower current density, one effect,e.g. leakage current, may be the dominant effect, but at higher currentdensity, e.g. charge crowding and other issues, may be the dominanteffect. As such, the bias may be modified accordingly to offer betterperformance. The bias may be adjusted as a single device or cluster ofdevices or the entire array of the devices. The bias may also bedifferent for different devices. For example: LED vs sensors, or red vsgreen LEDs may all have different biasing conditions.

Process of forming the MIS structure 112 on the micro device 100 isdescribed in FIGS. 2A to 2C. The order of these steps in these processesmay be changed without affecting the final results. Moreover, each stepmay be a combination of a few smaller steps.

With reference to FIG. 2A, in a first step 200, the micro devices 100are formed. During step 200, either the micro devices 100 are formed bypatterning or by selective growth. During step 202 the micro devices 100are prepared for transfer. which may include cleaning or moving to atemporary substrate. During step 204, the MIS structure 112 is formed onone surface of the micro device 100. During step 206, the device 100again prepared for transfer, which may include a lift off process, acleaning process and/or other steps. In addition, during step 206,connection pads or electrodes for device function electrodes or for theMIS structure 112 may be deposited and/or patterned. During step 208,selected devices 100 are transferred to a receiver substrate. This maybe done by various methods, including but not limited to pick-and-placeor direct transfer. In step 210, connections are formed for the device100 and the MIS structure 112. In addition, other optical layers anddevices may be integrated to the system substrate after the transferprocess.

Another example of a process of forming the MIS structure 112 on themicro device 100, is illustrated in FIG. 2B. First the micro devices 100are formed in step 200. During step 200, the micro devices 100 may beformed by patterning or by selective growth. During step 202, the microdevices 100 are prepared for transfer, which may include cleaning ormoving to a temporary substrate. During step 204-1, part of the MISstructure 112 is formed, for example the deposition and patterning of adielectric, on one surface of the micro device 100. During step 206, themicro devices 100 are again prepared for transfer, which may include alift off process, cleaning process and/or other steps. In addition,during step 206, connection pads or electrodes for function of the microdevices 100 or for the MIS structure 112 are deposited and/or patterned.During step 208, selected micro devices 100 may be transferred to areceiver substrate. The transfer may be done by various methodsincluding but not limited to pick-and-place or direct transfer. The MISstructure 112 may then be completed during step 204-2, which may includedeposition and patterning of a conductive layer. During step 210,connections are formed for the micro devices 100 and the MIS structureor structures 112. Other optical layer and devices may be integrated tothe system substrate after the transfer process. Step 210 may be thesame as 204-2 or a different and/or separated step. Other process stepsmay also be executed between steps 204-2 and 210. In one example, apassivation or planarizer layer may be deposited and/or patterned priorto step 210 to avoid shorts between MIS electrodes and otherconnections.

With reference to FIG. 2C, another example of a process of forming MISstructure 112 on the micro device 100, is illustrated. First the microdevices 100 are formed in step 200. During step 200, the micro devices100 may be formed by patterning or by selective growth. During step 202,the devices 100 are prepared for transfer, which may include cleaning ormoving to a temporary substrate. In addition, during step 202,connection pads or electrodes for the function of the micro device 100and/or for the MIS structure 112 may be deposited and/or patterned.During step 208, selected micro devices 100 may be transferred to thereceiver substrate, which may be done by various methods, such as butnot limited to pick-and-place or direct transfer. The MIS structure 112is then formed during step 204, e.g. on the receiver substrate, afterthe final transfer, which may include deposition and patterning ofdielectric and conductive layers. During the following step 210,connections are formed for the micro devices 100 and the MIS structures112. In addition, other optical layer and devices may be integrated tothe system substrate after the transfer process. Step 210 may share someof the same process steps with step 204 or be a completely separatedstep. In later case, other process steps may be done between 204 and210. In one example, a passivation or planarized layer may be depositedand/or patterned prior to step 210 to avoid shorts between MISelectrodes and other connections.

After patterning the micro devices 100, depending on the patterningprocess, each micro device 100 may have straight or sloped walls. Thefollowing descriptions are based on selected sloped embodiments, butsimilar or modified processing steps may be used for other embodimentsas well. In addition, depending on the transfer method, each microdevice face connected to receiver substrate may vary and so affect theslope of the device wall. The processing steps next described may beused directly or modified to be used with other slopes and devicestructures.

FIG. 3 illustrates a plurality of micro devices 306, similar to microdevices 100, which have been transferred to a system or receiversubstrate 300. The micro devices 306 include side wall of faces with anegative slope, i.e. at an acute angle with a top of the micro device306 and an obtuse angle with the bottom of the micro device 306 or withthe system substrate 300. Each micro device 306 is connected to acircuit layer 302 through at least one contact pad 304. Depending on theslope of the side walls, an MIS structure may be formed using normaldeposition or polymer deposition. The methods described herein may beused with some modifications or directly for this case. However, if theslope is too steep, the preferred way is to prepare the MIS structure onthe micro devices 306 prior to transfer. An exemplary method forcreating MIS structure prior to transfer will be described hereinafter.

FIG. 4 illustrates a process flowchart for a basic wafer etching process1000 for mesa structure formation. In step 1001 the wafers may becleaned, e.g. using piranha etching containing sulfuric acid andhydrogen peroxide, followed by a hydrochloric diluted DI water cleaningstep. Step 1002 may include deposition of a dielectric layer. In step1006 the dielectric layer may be etched to create an opening on thelayer for subsequent wafer etching. In step 1008 the wafer substrate maybe etched using dry etching technique and chlorine chemistry to developmesa structures. In step 1010, hard mask may be removed by wet or dryetching method, and the wafer may then be subsequently cleaned in step1012.

Embodiments of a method of forming an MIS structure in accordance withprocess 1000 are illustrated with reference to FIGS. 5A to 5D. The microdevices 406 may include a vertical side-wall structure, a negative slopeside-wall structure or a positive slope side-wall structure, i.e. thesidewalls are at an acute angle with the base of the micro device 406and the system substrate 400. In FIG. 5A, each of the micro devices 406are transferred to a system substrate 400, and connected to a circuitlayer 402, which is formed or mounted on the system substrate 400,through at least one connection pad 404. After this step, the MISstructure may be initiated and completed or simply completed. Whiletraditional lithography, deposition and patterning processes areapplicable for creating or completing such structure and for connectingthe micro devices to proper bias connections, different methods may beused with further tolerance to misplacement of the micro devices.Specially, in large area processes, the micro device placementinaccuracy may be a few micrometers.

With reference to FIG. 5B, in this embodiment a dielectric layer 408 maybe deposited around the micro devices 406 to cover unwanted exposedportions of the contact pads 406. Openings for vias 418 may be formed,e.g. etched, in the dielectric layer 408 for connecting a conductivelayer 412 of the MIS to the circuit layer 402. A similar or differentdielectric layer 410 may be deposited on at least one side of each ofthe micro devices 406, as part, i.e. insulator part, of the MISstructure. The dielectric layer 410 deposition step may be conductedprior to transferring the micro device 406 to the system substrate 400,at the same time as the dielectric layer 408 or after layer 408.Subsequently, the conductive layer 412 may be deposited and patternedaround and between each micro device 406, completing the MIS structure.In an embodiment, the conductive layer 414 may connect at least twomicro device/MIS structures together. In addition or alternatively, theconductive layer 416 may connect the MIS structure to a contact pad 406of the micro device 404. The conductive layer 412 may be transparent toenable other optical structures to be integrated into the systemsubstrate 400. Alternatively, the conductive layer 412 may be reflectiveto assist light extraction, direction, reflection or absorption. Theconductive layer 412 may also be opaque for some applications. Furtherprocessing steps may be carried out after formation of the MISstructure, such as but not limited to depositing common electrode,integration of optical structure/devices.

FIGS. 5C and 5D illustrate an exemplary structure for depositing acommon electrode 426 on an opposite side of the MIS structure to thesystem substrate 400. The upper surface of the MIS structure isplanarized, e.g. using a dielectric material, similar to dielectriclayer 408, and then patterned, e.g. etched, to provide access points forconnection of the common electrode 426 to the micro devices 404. Thecommon electrode 426 may be coupled to either the micro device 406, theMIS structure (conductive layer 412) or the circuit layer 402 throughthe patterning, e.g. openings 420, 422 and 424.

The common electrode 426 may be transparent to light from micro devices406 to enable the light to pass therethrough, reflective to the lightfrom the micro devices 406 to reflect the light back through the systemsubstrate 400 or opaque to the light from the micro devices 406 tominimize reflection. The common electrode 426 may also be patterned tocreate addressable lines. Several other methods may be used for thedeposition of the common electrode 426. Other optical devices andstructures may be integrated onto the system substrate or into thecircuit layer before or after the common electrode 426.

With reference to FIGS. 6A to 6C, an alternative process includesforming part or most of the MIS structure on a donor (or intermediate ororiginal) substrate 560 prior to transferring micro devices 504 to asystem substrate 500. The initial process steps may be conducted on theoriginal substrate used for fabrication of the micro devices 504 or onany intermediate substrate. With reference to FIG. 6A, a dielectriclayer 516 may be deposited prior to the formation of the MIS structure,which may avoid any unwanted short/coupling between the MIS layer andthe other contacts after transfer. The MIS structure is formed by aconductive layer 512 and a dielectric layer 510 deposited around andbetween the micro devices 504. The dielectric layer 510 may be similarto dielectric layer 516 or different. The dielectric layer 510 may alsobe a stack of different dielectric material layers. In example MISstructures 550 and 552, no top dielectric layer 518 is deposited on topof the conductive layer 512. In example MIS structure 552, theconductive layer 512 is recessed down from the top edge of the microdevice 504 to avoid any short with a top electrode; however, theconductive layer 512 may cover the top edge of the micro device 504, ifdesired. In example MIS structure 554, the conductive layer 512 mayinclude a wing portion extended outwardly from an angled portionparallel to the donor substrate 560 beyond a dielectric layer 518 tocreate easier access for creating connection after transferring to asystem substrate. In addition, the micro device 504 may be covered withthe dielectric layer 518 with openings for connection to the microdevice 504 and the extended electrode 512. Example MIS structure 556 mayuse the dielectric 518 for covering only the top side of the conductivelayer 512 and the micro device 504, except for an opening for the topelectrode to contact the micro device 504.

FIGS. 6B and 6C illustrate the micro devices 504 with MIS structuresafter being transferred to the system substrate 500. During the transferprocess, the micro devices 504 may be flipped so that the bottom surfaceconnected to the donor substrate 560 is also connected to the systemsubstrate 500. A connection pad 506 may be provided between each microdevice 504 and the system substrate 500 to couple the micro devices 504to the circuit layer 502. Different methods may be used including theone described above to create a connection for the MIS structure andother electrodes, e.g. a common electrode. In another embodiment, theexample MIS structures 550 and 552 include a top electrode 541 coveringboth the micro device 504 and the conductive layer 512 of the MISstructure. The top electrode 541 may be connected to the circuit layer512 with a via 532 extending through the dielectric layer 516 or theelectrode 541 may be connected at the edge of the system substrate 500through bonding. In example MIS structure 554, an extension 540 of theconductive layer 512 may be used to couple the MIS structure, i.e. theconductive layer 512, to the circuit layer 502. The dielectric layer 516may be extended on the system substrate 500 to cover the connection pads506 between micro device 504 and the system substrate 500 avoidingpossible short between the MIS structure and other connections. A topelectrode 542 may be provided, as in example MIS structures 554 and 556,which extends through an opening in the top dielectric layer 518 intocontact with the micro device 504. With regards to example MIS structure556, the MIS, e.g. the conductive layer 512, may be shorted to thedevice contact pads 506 or the MIS may be aligned properly to have itsown contact on the system substrate 500. For both example MIS structures554 and 556, different post processing steps may be used, similar toother structures disclosed herein. One example may be a common electrodedeposition with or without planarization, as in FIG. 5D. Another examplemay be light confinement structure or other optical structures.

FIGS. 7A and 7B illustrate an alternative process, in which part or mostof the MIS structure are formed on the donor (or intermediate ororiginal) substrate 560 prior to transferring them to the systemsubstrate 500. The process may be done on the original substrate usedfor fabrication of the device or on any intermediate substrate. FIG. 7Aillustrates several different example MIS structures 650, 652 and 654,which may be formed on micro devices 604; however, other structure maybe used as well. A dielectric layer 616 may be deposited prior to theformation of the MIS structures, which may avoid any unwantedshort/coupling between the MIS structure and other contacts aftertransfer. The MIS structure includes a conductive layer 612, and adielectric (insulating) layer 610. The dielectric layer 610 may besimilar to 516 or different. The dielectric layer 610 also may be astack of different dielectric material layer. In addition, a connectionpad 614 may be formed on each micro device 604 extending through anopening in the dielectric layer 610. In example MIS structure 650 and652, no dielectric may be deposited on top of the conductive layer 612.However, in example MIS structure 654 an additional layer of dielectric618 may be provided for planarization and extra insulation between thecontact pad 614 and the conductive layer 612. In example MIS structure652, the conductive layer 612 may be contiguous, e.g. the same, as thecontact pad 614. The conductive layer 612 may be recessed from the edgeof the micro device 604 or the conductive layer 612 may cover the edgeof the device 604. In structure 654, the conductive layer 612 includesan extension extending parallel to the system substrate 660 to createeasier access for creating connection after transferring to systemsubstrate 660. In addition, the micro device 604 may be covered with adielectric layer 618 with openings for connection of the contact pad 614to the micro device 604 and the extended electrode 612 to the systemsubstrate 660.

FIG. 7B illustrates the micro devices 604 with MIS structures afterbeing transferred to the system substrate 600. A connection pad 606 maybe provided between each micro device 604 and the system substrate 600to couple each micro device 604 to the circuit layer 602. Differentmethods may be used, including the ones described above, to createconnections between the MIS structures and other electrodes, e.g. acommon electrode. Another method is illustrated in FIG. 7B, for MISstructure 650 and 654, in which the negative slope of the micro device604 is used to create connection between the MIS structures 650 and 654and the system substrate 600 through an electrode 618 extending from theconductive layer 612 parallel to the system substrate 600 along the topof the dielectric layer 621. A conductive metal via 620 may extendthrough a passivation or planarization, e.g. dielectric, layer 621, intocontact with the circuit layer 602. The passivation or planarizationlayer 621 may be deposited prior to the electrode 618 deposition andpatterning. The micro device 604 may be covered during electrodedeposition or the conductive layer 612 may be removed from the top ofthe micro device 604 by patterning and etching. Using the negative slopeof the micro device 604 and the conductive layer 612 for separating thetop electrode 622 of the micro device 604 and the MIS electrode 618,minimizes misalignment therebetween, which is crucial for highthroughput placement of the micro devices 604. The negative slope of theside face of the micro device 604 and the conductive layer 612 forms anacute angle with the circuit layer 602 and the system substrate 600. Forall structures, different post processing steps similar to otherstructures disclosed herein. One example may be a common electrodedeposition with or without planarization. Another example may be lightconfinement or reflective structure or other optical structure.

The methods described herein may be used for different structures andthe methods are just examples and may be modified without affecting theoutcome. In one example, any one of the top and bottom electrodes 622and 614 and the conductive layers 612 may be either transparent,reflective or opaque. Different processing steps may be added betweeneach step to improve the device or integrate different structure intothe device without affecting the outcome of creating the MIS structure.

Vertical Devices with Conductivity Modulation Engineering

FIG. 8A illustrates a schematic of a vertical solid-state micro device,similar to micro devices 406, 504 and 604, showing lateral currentcomponents flowing from a top electrode layer, which is capable ofdirecting current through the bulk of the micro device in a device layer701. The device layer 701 is formed on a device substrate 700 withcontact pads 703, i.e. the top electrode, formed, e.g. etched, on thedevice layer 701. A voltage source 704 may be connected to the contactpads 703 and a common bottom electrode 702, mounted on the devicesubstrate 700, for generating the current to power the micro devices.The functionality of device layer 701 is predominantly defined by thevertical current. However, due to the top surface lateral conduction ofthe device layer 701, current 705 with lateral components flow betweenthe contact pads 703 and the common electrode 702. In order to reduce oreliminate the lateral current flow 705, the following techniques aresuggested:

1. Top layer resistance engineering

2. Fully/Partial etching modulation

3. Material conductivity modulation

In this way, the lateral current flow structure may be divided intothree main structures: 1) at least one conductive layer 703 withresistance engineering; 2) a full or partial etching of one or moreconductive layers 703, and 3) a material for conductivity modulation,e.g. alternating conductive and non-conductive sections or conductivesections separated by non-conductive sections.

The conductive layer 703 with resistance engineering may be described asfollows. The semiconducting top layer of the device layer 701, justbefore the metallic contact 703, may be engineered to limit the lateralcurrent flow by manipulating the conductivity or thickness of theconductive layer 703. In one embodiment, when the top layer of thedevice layer 701 is a doped semiconducting layer, decreasing theconcentration of active dopants and/or the thickness of the layer maysignificantly limit the lateral current flows. Also, the contact areamay be defined to limit the lateral conduction. In another case, thethickness of the conductive layer 703 (or more than one conductivelayers) may be reduced. After that the contact layer 703 may bedeposited and patterned. The deposition of the contact layer 703 may bedone on an array of interconnected or contiguous micro devices or onnon-isolated micro devices. As a result, the active layers of the devicelayer 701 are not etched or separated to create individual microdevices, therefore, no defect is created at the perimeter of theisolated micro devices, since the isolation is developed electrically bycontrolling the current flow.

Similar techniques may be used on isolated micro devices to diverge thecurrent from the perimeter of each micro device. In another embodiment,after the micro device is transferred to another substrate, the otherconductive layer or layers are exposed. The thickness of the devicelayer 701 may be chosen to be high to improve device fabrication. Afterthe contact layer 703 is exposed, the thickness may be reduced, or thedopant density decreased; however, some of the contact layers 703 mayalso have a blocking role for the opposite charge. As a result, removingsome of the conductive layers of the contact layer 703 to thin the totalcontact layer resistance may reduce the device performance. However,conductive layer removal may be very efficient on single layerengineering.

With reference to FIG. 8B, another embodiment of a micro devicestructure in accordance with the present invention includes a partiallyetched top layer 716 of a micro device layer 718. In this embodiment,the top conductive layer 716 may be for example a p-or-n-doped layer ina diode. The material for conductivity modulation directs currentthrough the bulk of vertical solid-state device in the device layer 718.At least one of the conductive layers, e.g. top conductive layer 716, inthe device layer 718 may be partially or fully etched formingalternating raised conductive layer sections and open non-conductiveareas. The top conductive layer 716 below top contact 712 and on top ofthe device layer 718 may be fully or partially etched to eliminate orlimit the lateral current flow in the micro devices 714 formed in thedevice layer 718. Each micro device 714 is defined by the size of thetop contact pad 712. This is especially beneficial for micro devices 714in which the resistance manipulation of the top layer 716 will adverselyaffect the device performance. The thickness of the top conductive layer716 between adjacent devices 714 is reduced to make a higher resistancefor the current to flow in the lateral direction. An etching process maybe done using, for example, dry etching, wet etching or laser ablation.In many cases, the top contact 712 may be metallic and/or used as themask for the etching step. In case of full etching, the etching may stopat a function layer of the device layer 718. In one embodiment, the topcontact 712 may be deposited on top of the conductive layer 716, and maybe used as the mask for etching the conductive layer or layers 716,potentially enabling fewer processing steps and a self-alignedstructure. This is especially beneficial for micro devices 714 in whichthe resistance manipulation of the conductive layer 716 will adverselyaffect the vertical device performance. In this embodiment, thethickness of the conductive layer 716 is reduced in selected areas tomake a higher resistance for the current to flow in the lateraldirection. After the bottom conductive layers of the device layer 718are exposed either by transfer mechanism or etching of substrate 710,the same etching process may be performed. Again, the contact 712 may beused as the mask for etching the device layers 716 and 718.

With reference to FIG. 8C, another embodiment of a micro devicestructure in accordance with the present invention includes a topconductive modulation layer 722 on the device layer 718. As shown, theresistance of a (non-conductive or reduced-conductive) modulation area720 of the top conductive modulation layer 722 between adjacent contactpads 712 is manipulated, e.g. increased to greater than conductive layer722 to limit the lateral current flow components. Counter doping, ionimplantation, and laser ablation modulation are examples of processesthat may be used to form the modulation areas 720 in this embodiment.The ion implantation or counter doping may extend beyond the conductivelayer 722 into the device layer 718 to further enhance the isolationbetween the current flowing through adjacent micro devices 714. Similarto the full/partial modulation scheme, in this embodiment the topcontact 712 may deposited on the top conductive layer 722 first, andthen used as a mask for the doping/implantation of the areas 720. Inanother embodiment, oxidation may be used to form the modulation areas720. In one method, a photoresist is patterned to match the modulationarea 720, then the devices are exposed to oxygen or other chemicaloxidant to oxidize the modulation areas 720. Then the top contacts 712may be deposited and patterned. In another method, the top contacts 712are deposited and patterned first, then the top contact 712 is used asmask the micro devices 714 for oxidation of the modulation areas 720.The oxidation step may be done on isolated devices or non-isolateddevices. In another embodiment, prior to oxidation, the total thicknessof the conductive layer(s) 722 may be reduced. The reduction step may bedone on selected modulation areas 720 for oxidation only. In anothercase, the oxidation may be done on the walls of the micro devices 714,which is especially applicable for isolated devices. Also, the bottomlayer of the device layer 718 may be modulated similarly after beingexposed. In another embodiment, the material conductivity modulation maybe done through electrical biasing. The bias for the areas 720 thatrequire high resistance is modified. In one embodiment, the effect onthe areas 720 may be extended to the device layers 718. Here, theconductive layer 722 may be modified, e.g. etched or implantation, withother methods described herein, as well. In one embodiment, charge maybe implanted underneath area 720 inside device layers 718. Theimplantation may be partial or all the way to the other side of thedevice layer 718.

In one embodiment, the bias modulation may be provided using an MIS(metal-insulator-semiconductor) structure, and the metal layer may bereplaced with any other conductive material. For example, to prevent thecurrent from the contact 712 from going further away from the contactlaterally, an MIS structure is formed around the contact 712. The MISstructure may be formed before or after the contact is in place. In allabove-mentioned embodiments, the area of the active micro device 714 isdefined by the top contact pads 712 formed on the device layer 718.

The definition of the active device area by the top contact pad 712 maybe more readily applied to micro devices 714 with pillar structures.FIG. 8D illustrates a cross section of an MIS structure surrounding asingle contact layer 712; however, it is understood that the same may bedone for more than one contact layer 712. The device layer 718 is amonolithic layer comprising or consisting of pillar structures 722.Because the pillar structures 722 are not connected laterally, nolateral current component exist in the device layer 718. One example ofthese devices is nanowire LEDs, in which each LED device consists ofseveral nanowire LED structures fabricated on a common substrate 710. Inthis case, as it is shown in FIG. 8D, the top metallic contact 712defines the active area of the LED structure 714. Device layers 718 withno lateral conduction is not limited to pillar structures, and may beextended to device layers 718 with separated active regions, such aslayers with embedded nano or micro spheres or other forms.

With reference to FIG. 8E, another embodiment of a micro devicestructure in accordance with the present invention includes an MISstructure 715 surrounding the contact layer 712. The MIS structure 715comprises a top conductive layer 716, a middle insulator, e.g.dielectric, layer 717, and a bottom semiconductor layer 723, which maybe a top layer of the device layer 718. By biasing the conductive layer716 of the MIS structure 715 to an off voltage, limited or no currentwill pass the MIS structure 715 laterally. The MIS structure 715 may beformed on the device layer 718 or may be part of the transferredsubstrate, and the MIS structure 715 defines the direction of lateralconduction. Other configurations are conceivable, such as the conductivelayer 716 may extend to both sides of MIS structure 715, such that thedielectric 717 may extend over other conductive layers 712. The MISstructure 715 may be an open or closed structure, or alternativelycontinuous or a one-piece structure. In another embodiment, thedielectric 717 may comprise the oxidation layers from a photoresist ormasking step. Another dielectric may be deposited on top of theoxidation layer, or a deposited dielectric may be used by itself. Inanother embodiment, the conductive layer(s) 716 may be removed so thatthe dielectric 717 is in contact with a semiconductor layer 723. The MISstructure 715 may also be formed on the walls of the micro device 714for further deterring current from travelling to the edge of the microdevice 714. The micro device surface may also be covered by dielectric.For example, a gate conductive layer may be deposited and patterned fora gate electrode 716, then a dielectric 717 may be patterned using thegate electrode 716 as a mask. In another method, the dielectric 717,which is an insulator, is patterned first, and then the gate electrode716 is deposited after. The gate electrode 716 and the contact 712 maybe patterned at the same time or may be done separately. A similar MISstructure may also be made on the other side of the device layer 718after it is exposed. The thickness of conductive layers 716 of the microdevice 714 may be reduced to improve the effectiveness of the MIS 715.Where selective etching or modulation of the conductive layer 716 oneither side of the vertical micro device 714 is difficult, the MISmethod may be more practical, in particular if etching or resistancemodulation may damage the active device layer 718. In the describedvertical structures, the active device area 714 is defined by the topcontact area 712. Here, the ion implantation in the dielectric 717 orthe charge storage in a floating gate 716 may be used to permanentlybias the MIS structure 715.

FIGS. 8F and 8G illustrates a structure highlighting the use of adielectric 712-1 between the contact pads 712. The contact pads 712define the micro devices in a device layer 701 on top of a substrate700, which may be sapphire or any other type of substrate. The microdevices include a conductive layer 702 and a contact pad 712. Withreference to FIG. 8F, the conductive layer 702 is intact, but in FIG. 8Gthe conductive layer 702 is either etched, modified, or doped betweeneach contact pad 712 with different carrier or ions. Some extra bondinglayers 712-2 may be placed on top of the contact pads 712, or thecontact pads 712 may comprise the bonding layers 712-2. The bondinglayers 712-2 may be for eutectic bonding, thermocompression oranisotropic conductive adhesive/film (ACA/ACF) bonding. During thebonding, the dielectric layer 712-1 may prevent the contact pads 712from expanding to other areas and create contacts. In addition, thedielectric layer 712-1 may also be a reflector or a black matrix toconfine the light further. This embodiment is applicable to theembodiments demonstrated in FIG. 8-11 and all other related embodiments.The methods described here can be applied to either side of the microdevices.

Method for Manufacturing LED Displays

Methods for manufacturing LED displays are described using LED devicesgrown on a common, e.g. sapphire, substrate. Each LED may comprise asubstrate 750, a first doped conductive layer 752, e.g. n-type layer,active layers 754, and a second doped conductive layer 756, e.g. p-typelayer, formed on the substrate 750. The following is described withreference to a Gallium Nitride-based (GaN) LED; however, the presentlydescribed vertical device structure may be used for any type of LEDswith different material systems.

With reference to FIG. 9A, the GaN LEDs are fabricated by depositing astack of material on the sapphire substrate 750. The GaN LED deviceincludes the substrate 750, such as sapphire, an n-type GaN layer 752formed on the substrate 750 or a buffer layer (for example GaN), anactive layer 754, such as multiple quantum well (MQW) layer, and ap-type GaN layer 756. A transparent conductive layer 758, such as Ni/Auor ITO, is usually formed on the p-doped GaN layer 756 for a betterlateral current conduction. Conventionally, a p-type electrode 760, suchas Pd/Au, Pt or Ni/Au is then formed on the transparent conductive layer758. Because the substrate 750 (Sapphire) is an insulator, the n-typeGaN layer 752 is exposed to make an n-contact 762 to the n-type layer752. This step is usually done using a dry-etch process to expose then-type GaN layer 752 and then deposit the appropriate metal contacts forthe n-contact 762. In LED display applications where display pixels aresingle device LEDs, each LED is bonded to a driving circuit whichcontrols the current flowing into the LED device. Here, the drivingcircuit may be a thin film transistor (TFT) backplane conventionallyused in LCD or organic light-emitting diode (OLED) display panels. Dueto the typical pixel sizes (10-50 μm), the bonding may be performed at awafer level scale. In this scheme, an LED wafer, comprised of isolatedindividual LED devices, may be aligned and bonded to a back-plane whichis compatible with the LED wafer in terms of pixel sizes and pixelpitches. Here, the LED wafer substrate may be removed using variousprocesses such as laser lift-off or etching.

FIG. 9B illustrates a fabrication process of an LED display, includingthe integration process of a device substrate 801 with micro devices ina device layer 805, defined by top contacts 802, and bonding of thedevice substrate 801 to a system substrate 803. Micro devices aredefined using the top contact 802 formed on top of the device layer 805,which may be bonded and transferred to the system substrate 803 withcorresponding and aligned contact pads 804. For example, the microdevices may be micro LEDs with sizes defined by the area of their topcontact 802 using any methods explained above. The system substrate 803may be a backplane with transistor circuitry to drive individualmicro-LEDs. In this process, the LED devices are isolated by dry etchingand passivation layers. Full isolation of the devices may create defectsin the active or functional layers, reducing the efficiency and imposingnon-uniformities. Since the perimeter to area of the micro devices ismore substantial as the device becomes smaller, the effect of defectsbecome more noticeable. In one embodiment, a monolithic LED device isconverted into individual micro-LEDs without etching the active area andusing lateral conductive manipulation. As a result, there is no sidewall within the micro-LED to create defects. The surrounding wallsacross the array of LEDs may be thereby be extended until they have noeffect on the peripheral LED devices. Alternatively, a set of dummy LEDdevices around the array may be used to reduce the effect of theperipheral walls on the active micro-LED devices. This technique mayalso be used to prevent or reduce the current going through the sidewalls.

In another embodiment, illustrated in FIG. 9C, an LED wafer 850 may befabricated such that the device layer 805 includes a first dopedconductive, e.g. a n-type, layer 852 on a substrate 801 with the seconddoped conductive layer, e.g. p-type, layer 854 as the top layer, and themonolithic active layer 856 therebetween. Each contact 802 defines anillumination area 860. The thickness of the second doped conductive,e.g. p-type, layer 854 and conductivity may be manipulated to controlthe lateral conduction through the device. This may be done by eitheretching of the pre-deposited conductive layer 854 or by depositing athinner second, e.g. p-type, conductive layer 854 during the LEDstructure fabrication. For the etching method, accurate thicknesscontrol may be achieved using a dry etching process. In addition, thematerial structure of the second, e.g. p-type, layer 854 may be modifiedby layer doping level to increase the layer's lateral resistance. Thesecond doped conductive layer 854 does not have to be limited to thep-type layer and may be extended to other top layers in the LEDstructure. As a result of this modification, the illumination area 860may be defined solely by the area of the deposited contact layer 802 ontop of the p-type film 854.

In another embodiment illustrated in FIG. 9D, to further limit thelateral illumination, the second doped conductive layer, e.g. p-layer,854 between two adjacent pixels may be fully or partially etched. Thisprocess step may be done after the contact layer, e.g. contacts 802, isdeposited in a process such as dry etching. In this case, the contactlayer 802 may be used as a mask for etching the second conductive layer854. Preferably the present structures limits or eliminates the wallpassivation of pixels, which results in higher number of pixels in aspecific area of the wafer or higher pixels per inch (PPI). This mayalso be translated to fewer process steps and lower fabrication costcompared to fully isolated LEDs with wall passivation.

In another embodiment illustrated in FIG. 9E, an LED wafer structure isdefined by the top contacts 802 and a sub divided second dopedconductive, e.g. p-type, layer 854 including individual sectionsdefined, by e.g. laser etching. Here, the second conductive layer 854,e.g. p-type, may be partially or fully removed using laser ablationetching of the top conductive material, e.g. GaN. In this case, laserfluence defines the ablation rate, and any thickness of the secondconductive, e.g. p-type GaN, layer 854 may be etched precisely. Oneexample of such a laser is a femtosecond laser at red or infra-redwavelengths. Here the top metal contacts 802 or other protective layersare used as a mask in the laser etching process steps. Alternatively,the laser beam size may be defined using special optics to match thedesired etching region dimensions. In another example, shadow masks maybe used to define the sections of the second conductive layer 854, i.e.the etching regions, between contacts 802. Laser ablation etching mayalso be extended to the other layers, e.g. at least one of the activelayer 856 and the first conductive, e.g. n-type, layer 852, of the LEDstructure. In this case, the individual LED devices may be isolatedfully or partially from each other. In this scenario, it may be requiredto passivate LED etched walls by depositing dielectric layers.

In the above-mentioned embodiments contacts 865 for the first conductivelayer 852, e.g. n-layer contacts, may be formed after the firstconductive layer 852 is exposed either by bonding and removing the LEDwafer substrate 801 for connecting to the backplane circuitry 803 or anyother substrate, or by etching the substrate 801. In this embodiment,the first, e.g. n-type layer contact 865 may be a transparent conductivelayer to enable light illumination therethrough. In this embodiment, thefirst, e.g. n-type, layer contact 865 may be common for all or part ofthe bonded LEDs, as shown in FIG. 9F, which illustrates a LED wafer, asherein before described with particular reference to FIGS. 9C to 9E,with the substrate 801 removed and replaced with a common transparentn-contact 865, and the contacts 802 bonded to bonding pads 804 of thebackplane structure 803. In cases where the LED device structure isgrown on a semiconductor buffer layer, for example an undoped GaNsubstrate, in place of substrate 801, after the LED transfer processthis buffer layer may be removed to access the first conductive, e.g.n-type, layer 852. In the embodiment shown in FIG. 9F, the entire GaNbuffer layer is removed using processes such as dry/wet etching. Asdemonstrated in FIG. 9G, in another embodiment the first conductive,e.g. n-type, layer 852 may be connected to the common electrode 865 viaa layer of alternating dielectric sections 871 and doped conductivesections, e.g. n-type, 872, with the conductive sections 872 superposedover a corresponding contact 802, defining the illumination areas. Thesecond conductive, e.g. p-type, layer 854 may be connected to thecontacts 802. In another embodiment, both the first, e.g. n-type and thesecond, e.g. p-type, layers 852 and 854 may be connected to acontrolling electrode, e.g. 865, or a backplane, e.g. 803, for furtherpixelation.

FIG. 10A illustrates an integrated device 900 with micro devices definedby top contacts 903 bonded to a system substrate 904, which may includebonding pads 905. A common electrode 906, may be formed on top of thestructure. After transferring and bonding the device layer 902, whichcomprises a first conductive, e.g. n-type, layer, a second conductive,e.g. p-type, layer and a active layer therebetween, a common topelectrode 906 may be deposited on the structure. For some optical devicelayers, the common top electrode 906 may be a transparent or areflective conductive layer. The second conductive, e.g. p-type, layermay be thinned to reduce the light scattering effect before depositingthe top contacts 903. In addition, a bank structure, with alternatingfirst conductive material sections, n-type, and dielectric sections, maybe used to define the pixels where the wall of the banks (dielectriclayer) are opaque or reflective layers, as described with reference toFIG. 9G.

With reference to FIG. 10B, in an alternative embodiment, the LED wafer900 includes a buffer, e.g. dielectric, layer 908 and one or more commonmetallic contacts 910, e.g. n-contact vias, extending through the bufferlayer 908 into contact with the device layer 902, e.g. first conductive,e.g. n-type, layer. The integrated device 900′ includes micro devicesdefined by top contacts 903 bonded to a system substrate 904, ideallyusing contact pads 905. The common electrodes 910 may be formed at theedges of the device layer 902 and through the buffer layer 908 on top ofthe device layer structure 902. As shown, the buffer layer 908 ispatterned around the edge thereby vias extending through the bufferlayer 908 to make metallic contacts to the first conductive, e.g.n-type, layer. The top layer of the integrated device layer structure902 may be a layer with low conductivity. For example, the top layer maybe a buffer layer used during the growth of the device layer 902. Inthis case, the common electrodes 910 may be formed by making viasthrough the buffer layer 908, for example at the edge of the structureavoiding the top buffer layer.

With reference to FIG. 10C a transferred LED wafer 900″ includes adevice layer 902 with a patterned first conductive, e.g. n-type, layer.Underneath the n-type layer is an active layer and a p-type layer, ashereinbefore described. To further decrease the lateral lightpropagation or adjust the device definition, the first conductive, e.g.n-type, layer is patterned by partially or fully removing the firstconductive layer forming open channel grooves 907 between firstconductive sections, using the same structure as the front metalliccontact 910. Alternatively, the thickness of the first conductive layermay be reduced. The first, e.g. n-type, contact may be formed bydepositing a transparent conductive layer on top of the device layerstructure 902. The integrated device 900″ with micro devices defined bythe top contacts 903 may be bonded to a system substrate 904. The top ofthe device layer structure 902 is patterned to isolate micro deviceselectrically. The other layers, e.g. active and second conductive,device layer 902 may be patterned or modulated to further isolate microdevices electrically and/or optically.

FIGS. 10D and 10E illustrates another embodiment of a transferred LEDwafer with a patterned first conductive, e.g. n-type, layer of thedevice layer 902. In cases where the buffer layer 908 is present, boththe buffer layer 908 and the first conductive, e.g. n-type, layer ispatterned with open channel grooves 907 between superposed firstconductive and buffer layer sections. In one embodiment the patternedgrooves 907 may be further processed and filled with a material thatimproves the light propagation through the patterned area. An example ofthis is surface roughening to suppress total internal reflection and areflective material to prevent vertical light propagation in the grooves907. The integrated device 900′″ comprises micro devices defined by topcontacts 903 bonded to a system substrate 904 via bonding pads 905. Thetop of the structure is patterned to isolate micro devices electricallyand optically and common contacts 910 are formed at the edge of thedevice layer structure 902. If the buffer layer 908 exists, to isolatemicro devices the buffer layer 908 needs to be patterned or modulated aswell. Similar to the embodiment shown in FIG. 10B, the common contacts910 may be formed for example at the edge of the active layer structure902 through vias in the buffer layer 908. In addition, color conversionlayer (or color filter layers) may be deposited on top of the patternedbuffer or conductive layers 908 and 902 to create a color display. Inone case, the color conversion layers (color filter layers) may beseparated by a bank structure that may be reflective as well.

An integrated device 900″″, illustrated in FIG. 10F, includes microdevices defined by top contacts 903 bonded to a system substrate 904with optical elements 914 formed in the grooves 907 between adjacentmicro devices. As shown, the open channel grooves 907 may be filled by alayer or an stack of optical layers 914 to improve the performance ofisolated micro devices. For example, in optical micro devices, theoptical elements 914 may comprise some reflective material to better outcouple the light generated by the micro devices in a vertical direction.

FIG. 10G illustrates another embodiment of a transferred LED wafer900′″″ including the device layer 902 comprising a first conductive,e.g. n-type, layer 921, a second conductive, e.g. p-type, layer 922, anda monolithic active layer 923 therebetween. The second conductive layer922 is electrically connected to the backplane 904 using the contacts903 and corresponding contact pads 905 on the backplane 904. The firstconductive layer 921 and the buffer layer 908 are patterned to form openchannel grooves 907 between raised first conductive layer portions. Ashereinbefore described, the grooves 907 may include light managementelements 914, e.g. reflective material to direct light vertically andprevent scattering between micro devices.

In LED display applications where display pixels are single device LEDs,each LED should be bonded to a driving circuit which controls thecurrent flowing into the LED devices. Here, the driving circuit may be aTFT (Thin Film Transistor) backplane 904 conventionally used in LCD orOLED display panels. Due to the typical pixel sizes (10-50 μm), thebonding may be performed at a wafer level scale. In an embodiment, anLED wafer comprises isolated individual LED devices aligned and bondedto the backplane 904, which is compatible with LED wafer, e.g. 900′,900″ etc., in terms of pixel sizes and pixel pitches. Here, the LEDwafer substrate may be removed using various processes, such as laserlift-off or etching. In this embodiment, it is important to isolate theLED devices by dry etching and passivation layers.

In another embodiment, illustrated in FIG. 10H, the original LED waferis fabricated with the second conductive, e.g. n-type, layer 922 as thetop layer. After the second conductive layer 922 is bonded to thebackplane 904 using the contacts 903 and the contact pads 905, theoriginal substrate is removed exposing the first contact, p-layer, 921.The thickness and conductivity of the first conductive, e.g. p-type,layer 921 is manipulated to control the lateral conduction. This may bedone by either etching of the deposited first conductive, e.g. p-type,layer 921 or by depositing a thinner p-layer forming alternating secondconductive layer sections 921 a and dielectric layer sections 925 duringthe LED device layer structure 902 fabrication. For etching scenario, anaccurate thickness control may be achieved using dry etching process. Inaddition, the material structure of the first conductive, e.g. p-type,layer 921 may be modified in terms of the layer doping level to formalternating high and low doped second conductive layer sections 921 a toincrease the layer's lateral resistance. The modifications to the toplayer are not limited to the first conductive, e.g. p-type, layer 921and may be extended to other top layers in an LED device layer structure902. As a result of this modification, the illumination area may bedefined solely by the deposited conductive layer area on top of thep-type film.

To further limit the lateral illumination, the second conductive, e.g.n-type, layer 922 between two adjacent pixels may be fully or partiallyetched. This process step may be done after the conductive layerdeposition in a process such as dry etching, as in FIGS. 9D and 9E. Inthis case, the contacts 903 in the contact layer may be used as a mask.One important advantage of this scheme is to eliminate the wallpassivation of pixels which results in higher number of pixels in aspecific area of the wafer, or higher pixels-per-inch (PPI). This mayalso be translated to the less process steps and lower fabrication costcompared to fully isolated LEDs with wall passivation.

FIG. 10H also shows an exemplary embodiment for integrating a colorfilter or color conversion layers 930 (and/or other optical devices) ontop of the top electrode 906. Here, individual color filter sections ofthe layer 930 may be separated by some bank (dielectric or insulatingmaterial) structure 931. The bank structure 931 may be reflective oropaque for ensuring the light remains in the light emitting areas abovethe contacts 903. The bank structure 931 may be the extension of thedielectric layer 925 used to separate second conductive layer sections921 a, as illustrated in FIG. 9I. In the embodiment of FIG. 10I, the topcommon electrode 906 includes recesses, extending upwardly adjacent tothe color filter sections 930, for receiving the bank/dielectricstructures 931/925 extending through both the second conductive layer921 and the color filter section layer 930.

Other layers may be deposited on top of the color conversion and/orcolor filter layers 930. The structures of FIGS. 10H and 10I may beapplied to other embodiments, for example any of FIGS. 9 and 10, inwhich any one or more of the n-type layer, the buffer layer, and thep-type layer are patterned, thinned or modulated with materialmodification techniques. The color conversion layer 930 may be comprisedof any one or more of materials, such as phosphors, and nano materials,such as quantum dots. The color conversion layer 930 may be a blanket orcover selected areas. In case of a blanket deposition, the bankstructure 931 may be eliminated. If the conductivity of underlying firstconductive, e.g. n-type, layer 921 is sufficient the top commonelectrode 906 may be eliminated.

With reference to FIG. 10J, the bank structure 931 may be replaced byfirst conductive layer sections 921 a, which extend from the firstconductive, e.g. n-type, layer 921. The first conductive, e.g. n-type,layer 921 may act as a common electrode or a common electrode 906 mayalso be provided. There may be a dielectric layer separating a part ofthe common electrode layer 906 from the first conductive layer sections921 a to create further pixel isolation. The color conversion layerand/or color filter layers 930 may be deposited on the first conductivelayer 921, although some other buffer layers may be used. The colorconversion/filter layers 930 may be conductive enabling the topelectrode 906 to power the device layer 923 or an additional conductivelayer 935 may be included adjacent to or along with the colorconversion/filter layers 930. The top electrode 906 may be deposited ontop of the color conversion/first conductive layer section 921 a layers,if the conductivity of the first conductive layer 921 with the contactstructure 902 is not sufficient. The top common contact 906 may betransparent to enable generated light to pass therethrough, reflectiveto reflect generated light back through the structure 902, or opaque toabsorb light and further enhance the pixel isolation.

In another embodiment, illustrated in FIG. 10K, the first conductivelayer 921 may be etched to create pillar sections forming a bank betweenthe color filter sections 930. The top and portions of the side walls ofthe pillar sections may be covered by the top electrode 906, reflectivelayers, or opaque layers. The valleys in the first conductive layer 921may be filled with the color conversion and/or color filter layers 930.An additional conductive layer 935, e.g. transparent, may be depositedonly at the bottom of the valleys or all over the area including theside walls to define the light emitting area. There may be a top commonelectrode 906 or other layer deposited over the entire structure 902,with raised sections extending into the valleys into contact with theadditional conductive layer of the color filter layers 930. There may bea dielectric layer separating a part of the common electrode layer 906from the first conductive layer sections 921 a to create further pixelisolation.

In another embodiment, illustrated in FIG. 10L, a second device layer902′ may be transferred and mounted on top of the first device layer902. The second device layer 902 includes an additional first conductivelayer 921′, an additional second conductive layer 922′, and anadditional active layer 923′. Additional contacts 903′ and 906′ are alsoprovided to supply power to the elimination areas. The stacked devices902 and 902′ may include a first planarization layer and/or dielectriclayer 940 around the first device layer 902 and between to the first andsecond devices 902 and 902′, and a second planarization and/ordielectric layer 941 around the second device layer 902′. In oneembodiment, the surface of the first device layer 902 is planarizedfirst. Then openings for electrical vias 945 may be opened, e.g. etched,in the first planarization layer 950 to create contact to the backplane904. The contact, i.e. the vias 945, may be at an edge or in the middleof the first device layer 902. The second contact layer 903′, comprisingtraces and islands, are then deposited and patterned on top of the firstplanarization layer 940. Finally, the second device layer 902′ istransferred on top of the second contact layer 903′. The process maycontinue for transferring additional device layers 902. In anotherembodiment, the top contact 906 of first device layer 902 may be sharedwith the bottom contact 903′ of the second device layer 902′. In thiscase, the planarization layer 940 between the first and second devicelayers 902 and 902′ may be eliminated.

In another embodiment illustrated in FIGS. 11A and 11B, a device layer952, originally fabricated on a device substrate 950 is mounted on asystem substrate 958 via substrate contact pads or bumps 954, which maydefine the micro device illumination areas. The micro devices in theintegrated structure are partially defined by the contact bumps 954 onthe system substrate 958. In this embodiment, the device layer 952 maynot have any top contact to define the micro device area. The devicelayer 952 on the substrate 950 is bonded to a system substrate 958 withan array of contact pads or bumps 954 separated by an insulation, e.g.dielectric, layer 956. The bonding may be made between the metalliccontact pads 954 and the device layer 952. This bonding process may beperformed using any bonding procedure, such as but not limited to theheat and/or pressure bonding or laser heating bonding. An advantage ofthis procedure is the elimination of the alignment process during themicro device transfer to the system substrate 958. The micro device size960 and pitch 962 is partially defined by the size of the contactpad/bump 954. In one example, the device layer 952 may be LED layers ona sapphire substrate 950 and the system substrate 958 may be a displaybackplane with circuitry required to drive individual micro-LEDs definedpartially by the contact bumps on the backplane.

FIGS. 12A and 12B illustrates another integration process of a devicesubstrate 950 and a system substrate 958. The micro devices in theintegrated structure is fully defined by the contact bumps 954 on thesystem substrate 958. To precisely define the micro device size 960 andmicro device pitch 962, a bank layer 965 may be deposited and patterned,e.g. etched, on the system substrate 958. The bank layer 958, which mayinclude openings around each contact pad 954, may fully define the microdevice size 960 and micro device pitch 962. In one embodiment, the banklayer 965 may be an adhesive material to fix the device layer 952 to theinsulation or dielectric layer 956, i.e. to the system substrate 958.

FIG. 12C illustrates the integrated device substrate 950 transferred andbonded to the system substrate 958, and FIG. 12D illustrates a commontop electrode 966 formed on top of the device layer structure 952. Afterbonding the micro device substrate 950 to the system substrate 958, themicro device substrate 950 may be removed using various methods, and thecommon contact 966 may be formed above the integrated structure 952. Incase of optical micro devices, such as but not limited to micro-LEDs,the common electrode 966 may be a transparent conductive layer or areflective conductive layer. The bank structure 964 may be used toeliminate the possibility of a short circuit between adjacent pads 954after a possible spreading effect due to pressure on the pads 954 duringassembly. Other layers, such color conversion layers, may be depositedafter the bonding.

FIGS. 13A and 13B illustrate another embodiment of an integratedstructure in which a device layer 952 is mounted on a system substrate958 using one or a plurality of bonding element 968 at the edge of thebackplane 958. In this embodiment, adhesive bonding elements 968 may beused at the edge of the backplane 958 to bond the device layer 952 tothe system substrate 958 or the insulation layer 956 of the device layer952. In one embodiment, the bonding elements 968 may be used totemporarily hold the device layer 952 to the system substrate 958 forthe bonding process of contact pads 954 to the device layer 958. Inanother embodiment, the bonding elements 968 permanently attach themicro device layer 952 to the system substrate 958.

FIGS. 14A to 14C illustrate another embodiment of an integration processof the device substrate 950 and the system substrate 958 with postbonding patterning of the device layer 952 and the common electrode 966.In this embodiment, the device layer 952 may be patterned to includeraised contact sections, e.g. 1.5×-3.0× the thickness of the remainderof the conductive layer, over the contact pads 954, after transferringto the system substrate 958. The patterning 970 may be designed andimplemented to isolate micro devices electrically and/or optically.After patterning the device layer 952, the common top electrode 966 maybe deposited on the device layer 952 formed around and on top of theraised contact sections. In the case of optical devices, such as LEDs,the common electrode 966 may be a transparent conductive layer or areflective conductive layer.

FIGS. 15A to 15C illustrate an alternative embodiment of an integrationprocess of the device substrate 950 and system substrate 958 with postbonding patterning, optical element, and common electrode 966 formation.As illustrated, after transferring and patterning the device layer 952,similar to FIGS. 14A to 14C, additional layers 970 may be depositedand/or formed between isolated micro devices to enhance the performanceof micro devices. In one example, the elements 970 may passivate thesidewalls of the isolated micro devices to help to vertical out couplingof light in the case of optical micro devices, such as but not limitedto the micro-LEDs.

In the embodiments illustrated in FIGS. 8 to 10 and all other relatedembodiments, a black matrix or reflective layer may be deposited betweenthe pads 703, 712, 954, 908, to increase the light output. A reflectivelayer or black matrix may be part of the electrode.

In the presently explained methods, a protective layer may be finallyformed on top of the integrated structure to act as a barrier andscratch resistance layer. Also, an opaque layer may be deposited afterthe micro device and patterned to form the pixel. This layer may sitanywhere in the stack. The opening will allow the light to go throughonly the pixel array and reduce the interference.

The micro devices as described herein may be developed, for example, byetching a wafer and forming mesa structures. Mesa formation may be doneusing dry or wet etching technique. Reactive ion etching (RIE),inductive coupled plasma (ICP)-RIE and chemical assisted ion beametching (CAIBE) may be employed for dry etching of the wafer substrate.Chlorine based gases such as Cl₂, BCl₃ or SiCl₄ may be used to etchwafer. Carrier gases including but not limited to Ar, O₂, Ne and N₂ maybe introduced into the reactor chamber in order to increase degree ofanisotropic etching and sidewall passivation.

With reference to FIGS. 16A to 16D, a device structure 1100 includes adevice layer 1202 deposited on a wafer surface 1200. Following the wafercleaning step, a hard mask 1206 is formed on the device layer 1202. Inan embodiment, a dielectric layer 1204, such as SiO₂ or Si₃N₄, is formedon the device layer 1202 using appropriate deposition technique, such asplasma-enhanced chemical vapour deposition (PECVD). The hard maskphotoresist 1206 is then applied on the dielectric layer 1204. In thephotolithography step, a desired pattern is formed on the photoresistlayer 1206. For example, PMMA (Poly(methyl methacrylate)) may be formedon the dielectric layer 1202 followed by a direct e-beam lithographytechnique to form the openings in the PMMA 1206.

FIG. 16B illustrates the device structure 1100 with the dielectric layer1204 etched to create openings on the device layer 1202 for subsequentwafer etching. A dry etch method with fluorine chemistry may be employedto selectively etch the dielectric layer 1204. Carrier gases, includingbut not limited to N₂, Ar, O₂, may be introduced to control the degreeof anisotropic etching. Gas flow rate and mixture ratio, type of carriergases, RF and dc powers, as well as substrate temperature may beadjusted to achieve desired etching rate and high degree of anisotropy.

FIG. 16C illustrates mesa structures 1208 and 1210 after the waferdevice layer 1202 etching step. In one embodiment, mesa structures 1208with straight side walls, e.g. perpendicular to the upper surface of thesubstrate 1200, may be formed. In another embodiment mesa structures1210 with sloped side walls, e.g. forming an acute angle with the uppersurface of the substrate 1200, may be formed. The gas mixture ratio,type of gases in the reactor and relevant etching conditions may beadjusted in order to modify the slope of the side walls. Depending onthe desired mesa structure 1208 and 1210, a straight, positive andnegative slope side wall may be formed. In an embodiment, sidewallpassivation during the etching step may be used to create a desiredsidewall profile. In addition, a cleaning step may be used to remove thepassivation layer or the native oxide from the side-wall. Cleaning maybe done using acetone, isopropyl alcohol followed by surface treatmentusing (NH₄)₂ and/or NH₄OH.

In an embodiment, a MIS structure may be formed after the mesa structureformation of FIGS. 16A to 16C. With reference to FIGS. 17 and 18A to18D, a process flow 1000B for formation of MIS structure, includesprocess steps 1114 and 1116, in which dielectric and metal layers 1402and 1404 are deposited on mesa structures, e.g. 1208 and 1210, to formMIS structures. Following the deposition of the dielectric layer 1402,in process 1116, a metal film 1404 is deposited on the dielectric layer1402 using a variety of methods, such as thermal evaporation, e-beamdeposition and sputtering (FIG. 18A). In process step 1118, a desiredpattern is formed on the wafer using photolithography step. In step1120, the metal layer 1404 is etched using dry or wet etching forming anopening on the top side of the mesa structure above the dielectric layer1402 (FIG. 18B). In step 1122, a photolithography step may be used todefine the dielectric etch area. In another embodiment the etched metallayer 1404 may be used as a mask for etching the dielectric layer 1402(FIG. 18C). In step 1126, a second dielectric layer 1406 may depositedon the metal interlayer 1404 (FIG. 18D). In step 1128, an ohmic, e.g.p-type, contact 1408 may be deposited on the micro device mesastructures 1208 and 1210, as shown in FIG. 18E. In process step 1130, athick metal 1410 is deposited on the contact 1408 for subsequent bondingof the mesa structures 1208 and 1210 to a temporary substrate in waferlift-off process steps from the native substrate.

FIG. 18A illustrates the dielectric layer 1402 and the metal layer 1404deposited on the mesa structure to form a MIS structure. A variety ofdielectric layers 1402 may be used, which include but are not limited toSi₃N₄ and oxides such as SiO₂, HfO₂, Al₂O₃, SrTiO₃, Al-doped TiO₂,LaLuO₃, SrRuO₃, HfAlO and HfTiO_(x). The thickness of the dielectriclayer 1402 may be a few nanometers up to a micrometer. A variety ofmethods, such as CVD, PVD or e-beam deposition, may be used to depositthe dielectric layer 1402. In an embodiment, a high-k oxide dielectriclayer 1402 may be deposited using atomic layer deposition (ALD) method.ALD enables very thin and high-K dielectric layers to be formed on thewafer. During ALD deposition of the dielectric oxide layer, precursorsare introduced in the reaction chamber sequentially to form a thininsulator layer. Metal precursors for the metal layer 1404 includehalides, alkyls and alkoxides and beta-deketonates. Oxygen gas may beprovided using water, ozone or O2. Depending on the process chemistry,dielectric film deposition may be done at room temperature or atelevated temperature. Deposition of Al₂O₃ may also be done usingtrimethylaluminum (TMA) and water precursors. For HfO₂ ALD deposition,HfCl₄ and H₂O precursors may be used. Metal electrodes 1410 serve asbiasing contacts for electric field modulation in the device. Metalcontacts 1408 include but not limited to Ti, Cr, Al, Ni, Au or metalstack layer.

FIG. 18B illustrates the wafer with a pattern formed using aphotolithography step. FIG. 18C illustrates the wafer with a dielectriclayer 1402 dry etched, e.g. using fluorine chemistry. An etch stop foretching the dielectric layer 1402 may be the top surface of the mesastructure 1208 and 1210. As illustrated in FIG. 18D, the seconddielectric layer 1406 may be deposited on the metal interlayer 1404 forsubsequent p-contact deposition in order to prevent shorting with devicefunctional electrode 1408 and 1410. Subsequently, the second dielectriclayer 1406 on top of the mesa structure may be etched to create anopening on the top surface of mesa structures.

With reference to FIG. 18E, the ohmic, e.g. p-type, contact 1408 maythen be deposited on the mesa structure to enable power from externalelectrical power sources to be input the micro devices. The contact 1408may be deposited using thermal evaporation, sputtering or e-beamevaporation. Au alloys such as Au/Zn/Au, AuBe, Ti/Pt/Au, Pd/Pt/Au/Pd,Zn/Pd/Pt/Au, Pd/Zn/Pd/Au may also be used for the contact 1408.Subsequent patterning step removes metal from unwanted areas allowingthe contact 1408 to be formed only on top surface of the mesastructures. A thick metal 1410 may deposited on the contact 148 forsubsequent bonding of mesa structures to temporary substrate in waferlift-off process steps from the native substrate.

The scope of this invention is not limited to LEDs. One can use thesemethods to define the active area of any vertical device. Differentmethods, such as laser lift-off (LLO), lapping, wet/dry etching may beused to transfer micro-devices from one substrate to another. Microdevices may be first transferred to another substrate from a growthsubstrate and then transferred to the system substrate. The presentdevices are further not limited to any particular substrate. Mentionedmethods may be applied on either n-type or p-type layer. For the exampleLED structures above n-type and p-type layers position should not limitthe scope of invention.

Although an MIS structure was disclosed in this document as the methodof manipulating electric field in the microdevice for manipulating thevertical current flow, one can implement other structures and methodsfor this purpose. In an embodiment, electric field modulation may bedone using a floating gate as a charge storage layer or conductivelayer. FIG. 19 illustrates an exemplary embodiment of a micro device1500 with a floating gate structure. The structure comprises a floatinggate 1514 that may be charged with different methods to bias the MISstructure. One method is using light source. Another method is using acontrol gate 1512 that is isolated with a dielectric layer 1516 from thefloating gate 1514. The biasing control gate 1512, enables charges to bestored in the floating gate 1514. Stored charges in the floating gating1514 manipulates the electric field in the device. When the micro device1500 is biased through the functional electrodes 1502 and 1504, thecurrent flows vertically resulting in the generation of light. Themanipulated electric field in the micro device 1500, limits lateralcurrent flow resulting in the enhancement of light generation.

FIG. 20 illustrates a schematic structure of the microdevice 1500 with afloating gate charge storage layer 1514. The illustrated microdevice1500 includes angled sidewalls as an example, but the microdevice 1500may include different, e.g. vertically, negatively and positively,angled sidewall. First, a thin dielectric layer 1516 is formed on themicrodevice 1500. The thickness of dielectric layer 1516 may be between5 nm to 10 nm to enable quantum mechanical tunneling of charges throughthe dielectric layer 1516. Oxide or nitride based dielectric materialsmay be used to form the thin dielectric layer 1516, including but notlimited to HfO₂, Al₂O₃, SiO₂ and Si₃N₄ etc. The floating gate 1514 maybe formed on the thin dielectric layer 1516. The floating gate 1514 maybe formed from thin poly-silicon or metal layer as a charge storagelayer. In another embodiment, the floating gate 1514 may be replacedwith dielectric material to form a charge trapping layer. The dielectricin the floating gate 1514 may be the same as the thin dielectric 1516 ora different layer. The dielectric layer of the floating gate 1514 may becharged by different techniques such as ion implantation. The dielectricmaterials including but not limited to HfO₂, Al₂O₃, HfAlO, Ta₂O₅, Y₂O₃,SiO₂, Tb₂O₃, SrTiO₃ and Si₃N₄ or combination of different dielectricmaterials to form a stack of layers may be used for the charge trappinglayer. In another embodiment semiconductor or metal nanocrystals orgraphene may be used as the charge trapping layer. Nanocrystalsincluding but not limited to Au, Pt, W, Ag, Co, Ni, Al, Mo, Si and Gemay be used for charging trap sites. The nanocrystals create isolatedtrap sites. This in turn reduces the chance of charge leakage due topresence of defects on the thin dielectric layer 1516. In addition, ifcharges leak from one nanocrystal, it will not affect the adjacent sitesas they are isolated from each other. On top of the floating gate orcharge trapping layer 1514, a second, thick dielectric layer 1518isolates the floating gate 1514 in order to prevent charge leakage. Thesecond dielectric layer 1518 may be made of various dielectricmaterials, including but not limited to HfO₂, Al₂O₃, HfAlO, Ta₂O₅, Y₂O₃,SiO₂, Tb₂O₃, SrTiO₃ with thickness of 10 nm to 90 nm. On top of thesecond dielectric layer 1518, a control gate 1512 is provided, which isresponsible for charging the floating gate 1514. The control gate 1512may be comprised of one or more conductive layers, such as metal,transparent conductive oxides, polymers, etc.

With reference to FIG. 21, a process flow 2000 of a development of afloating gate structure on the sidewalls of a micro-device 1500,includes a first step 1600 of forming the micro devices 1500, e.g. as inany of the methods hereinbefore described. During step 1600, either themicro devices 1500 are formed by patterning or by selective growth.During step 1602 the devices 1500 are transferred to a temporary orsystem substrate. During step 1604 the thin dielectric layer 1516 isformed on the micro-device 1500. In step 1606, the floating gate orcharge trapping layer 1514 is formed on the thin dielectric layer 1516.During step 1608, the second, thick isolation dielectric layer 1518 isformed on the floating gate 1514. In step 1610, the control gate 1512 isformed on the thick dielectric layer 1518. In step 1612, a protectivelayer is formed on the structure. The order of these steps in theseprocesses may be changed without affecting the final results. Also, eachstep may be a combination of a few smaller steps. For example, thestructure may be formed before the transfer process of microdevice 1500from donor substrate to the acceptor one. In another embodiment, partsof the floating gate structure may be formed before the microdevicetransfer process and the floating gate structure may be completed afterthe transfer step. In another embodiment the entire floating gatestructure may be formed after the micro device transfer step.

Accordingly, a process of forming a micro device with a floating gate orcharge trapping structure, comprises:

forming the micro devices including a functional electrode; and

forming a first dielectric layer or a charge trapping layer on a firstsidewall of the microdevice.

In addition, the process may include forming a floating gate layer or acharge trapping layer on the first dielectric layer.

In addition, the process may include forming a second dielectric layeron the floating gate or charge trapping layer.

In addition, the process may include forming a control gate on thesecond dielectric layer.

An alternative embodiment of the process, wherein the first dielectriclayer may be between 5 nm to 10 nm thick to enable quantum mechanicaltunneling of charges therethrough.

An alternative embodiment of the process, wherein the second dielectriclayer may be between 10 and 90 nm thick to isolate the floating gate inorder to prevent charge leakage.

An alternative embodiment of the process, wherein the floating gate maybe comprised of poly-silicon or metal layer as a charge storage layer.

An alternative embodiment of the process, wherein the charge trappinglayer comprises semiconductor nanocrystals, metal nanocrystals orgraphene.

An alternative embodiment of the process, wherein the nanocrystals maybe selected from the group consisting of Au, Pt, W, Ag, Co, Ni, Al, Mo,Si and Ge.

An alternative embodiment of the process, further comprising biasing thecontrol gate and the functional electrodes to generate an electric fieldenabling charges to be injected from a charge transport layer in themicrodevice into the floating gate through the thin dielectric layer.

An alternative embodiment of the process, wherein the charge injectioncomprises Fowler-Nordheim tunneling or hot electron injection mechanism.

An alternative embodiment of the process, wherein the charge injectionmay be conducted by photoexcitation of the charge transport layer.

An alternative embodiment of the process, wherein the charge injectioncomprises exposing the micro device to ultraviolet light resulting inhigh energetic charges that overcome a potential barrier between thecharge transport layer and the first dielectric layer.

An alternative embodiment of the process, wherein the floating gate orcharge trap layer formed on comprises a combination of two differentdielectric layers.

In an alternate embodiment, a first electrode contact extends from abottom contact layer of the micro-device on one side of themicro-device; a second electrode contact extends upwardly from a topcontact layer of the micro-device; and a third electrode contact extendsupwardly from the floating gate on another side of the micro-device.

In an alternate embodiment the first and third electrode contacts extendupwardly from a same side of the micro-device.

In an alternate embodiment the first and third electrode contacts extendupwardly from an opposite side of the micro-device.

In an alternate embodiment the first and second electrode contactsextend outwardly from opposite top and bottom surfaces of themicro-device.

Accordingly, another process of forming a micro device with a floatinggate or charge trapping structure, comprises:

forming the micro devices including a functional electrode; and

forming a first dielectric layer or a charge trapping layer on a firstsidewall of the microdevice.

In addition, the process may include charging the first dielectriclayer.

The process may include forming a second dielectric layer on the chargedfirst dielectric layer.

An alternative embodiment of the process, wherein the step of chargingthe first dielectric layer comprises ion bombardment creating fixedunneutralized charges on a surface of first dielectric layer.

An alternative embodiment of the process, wherein the ions are selectedfrom the group consisting of barium, strontium, iodine, bromine, andchlorine.

An alternative embodiment of the process, further comprising implantingsemiconductor ions in the first semiconductor layer to form a chargetrap layer.

An alternative embodiment of the process, wherein the semiconductor ionsmay be selected from the group consisting of Si+ and Ge+.

An alternative embodiment of the process, further comprising annealingthe first dielectric layer to cure stress on the dielectric layer afterion bombardment, and also enable diffusion of ions into the firstdielectric layer.

Accordingly, another process of forming a micro device with enhancedsidewalls compromises forming the micro devices including a functionalelectrode; and creating an intrinsic charges interface at the sidewallsby depositing semiconductor layers on a first side wall with differentband diagram compared to the sidewalls.

Referring to FIG. 22, a floating gate or charge trapping layer 1714 maybe charged employing a variety of methods. In one embodiment a controlgate 1706 and one of the functional electrodes 1702 or 1704 are biasedso that generated electric field allows charges 1708 to be injected fromthe highly doped charge transport layer in microdevice 1700 into thefloating gate 1714 through the thin dielectric layer 1716. Chargeinjection may be Fowler-nordheim tunneling or hot electron injectionmechanism. In the case of hot electron injection, charge injection maybe done by applying high voltage bias so energetic charges can overcomethe potential barrier between the charge transport layer and the thindielectric layer 1716. In another embodiment, charge injection may bedone by photoexcitation of the charge transport layer. In this case thedevice 1700 may be exposed to ultraviolet light resulting in highenergetic charges that can overcome the potential barrier between thecharge transport layer and thin dielectric layer 1714.

In another embodiment illustrated in FIG. 23, a floating gate or chargetrap layer 1810 formed on the first, thin dielectric layer 1816 may be acombination of two different dielectric layers. A biasing control gate1806, enables charging of an intermediate dielectric layer 1808. Thecharged intermediate dielectric layer 1808 creates image charges withopposite sign on the floating gate or charge trap layer 1810. With thistechnique the floating gate 1810 may be controlled to be positive ornegative allowing electric field propagation direction to be inward oroutward from the micro-device sidewall.

In another embodiment, illustrated in FIG. 24, an electric fieldmodulation structure may be formed without using a control gate. Adielectric layer 1906 is formed on the sidewall of a micro-device 1900.The formed dielectric layer 1906 may be permanently charged by ionbombardment or implantation forming a charge layer 1906. The chargelayer 1906 may be at either side or in the middle of the dielectriclayer 1908. Dielectric materials including but not limited to HfO₂,Al₂O₃, HfAlO, Ta₂O₅, Y₂O₃, SiO₂, Tb₂O₃, SrTiO₃ and Si₃N₄ or combinationof different dielectric materials to form a stack of layers may be usedfor charge trapping layer 1906. Ion bombardment creates fixedunneutralized charges in the charged layer 1906 hence creating anelectric field in the body of semiconductor. The ions may be positive ornegative, such as barium and strontium, iodine, bromine, chlorine etc.In addition, semiconductor ions such as Si+ and Ge+ may also beimplanted to form a charge trap layer. Following the ion implantation,the dielectric layer 1906 may be annealed to cure stress on thedielectric layer 1906 after ion bombardment, and also enable diffusionof ions into the dielectric layer 1906. Following the ion implantationand subsequent annealing, a thick dielectric layer 1908 is formed as anisolation and protective layer. The fixed charges in the dielectriclayer 1906 manipulates the electric field at thesemiconductor/dielectric layer interface pulling away charges in thesemiconductor from the interface toward the middle of device 1900limiting lateral current flow. Here, the ion/charge implantation may bedone directly in the dielectric layer 1906. A barrier layer may be usedbetween the dielectric layer 1908 and the micro device 1900 to protectthe micro device 1900 from the high energy ion particles during thecreation of charging layer 1906.

With reference to FIGS. 25A to 25D, in another embodiment related tobiasing an MIS structure 2016 on a micro device 2010, either electrode2012, 2014 of a micro device 2010 may be extended over the MIS gate (thegate may be an actual layer, e.g. conductive layer, or only a positionin a dielectric or other material to hold the charge) while a dielectriclayer 2018 a separates the MIS biasing gate and the micro deviceelectrode 2012. With reference to FIG. 25A, the contacts 2012 and 2014of the micro-device 2010 may extend upwardly. To create an MIS structure2016, i.e. including a gate, e.g. conductive layer, and a dielectriclayer, for such devices, a MIS contact 2022 to the MIS gate also extendsupwardly. This structure may simplify the process of integration of themicro-devices 2010 into a receiver substrate as similar bonding orcoupling process may be used for both MIS contact 2022 and the microdevice contacts 2012 and 2014. To avoid a short circuit between themicro-device 2010 layers and the MIS 2016 gate, a dielectric layer 2020a is deposited. The dielectric layer 2020 a may be part of the MISstructure or a separate dielectric layer deposited independently. Inaddition, to avoid shorts during the bonding and/or integration of themicro-device 2010 into a system (receiver) substrate, one or moredielectric layer 2018 a and 2018 b may cover the MIS structure 2016. Tocreate the contact to the micro-device 2010 for one of the electrodes2012 and 2014, the dielectric layer 2020 b may be removed or opened,e.g. etched. The dielectric layer 2020 b may be the same as any one ormore of dielectric layers 2018 b, 2020 a, and 2018 a, or a separatelayer altogether. The space between the contacts 2014, 2022, the MIS2016 and the micro-device 2010 may be filled with different type ofmaterials, such as polymer, dielectrics, etc. The filler may be the sameas the dielectric layers 2018 a and 2018 b or different. The position ofthe MIS contact 2022 and the micro-device contact 2014 may be differentrelative the micro-device 2010 or positioned symmetrically on eitherside thereof. In another embodiment, the MIS structure may be formedusing a charged layer and therefore no MIS contact 2022 will be needed.

FIG. 25B illustrates a top view of the micro-device 2010 with the MIScontact 2022 and the micro-device bottom contact 2014 located onopposite sides of thereof. In another embodiment demonstrated in FIG.25C, the MIS contact 2022 and the micro-device bottom contact 2014 arelocated on the same side of the micro-device 2010. In this case, thedielectric layers 2020 a and 2020 b may be the same layer 2020. Inanother exemplary embodiment illustrated in FIG. 25D, the MIS contact2022 and the micro device bottom contact 2014 are located on twoneighbouring side of the micro-device 2010. The micro-device 2010 mayhave other cross-sectional shapes, such as circle, and theaforementioned positions may be modified to accommodate the micro-deviceshape. The dielectrics 2018 and 2020 may be a stack of different layers,and the conductive (gate) layers may be either metal, any otherconductive material or stack of different materials.

FIG. 26 illustrates another embodiment of the micro device 2010 in whichthe contact for the MIS electrode 2022 and one of the device contacts(or pad) 2012 may be positioned on a first side, e.g. top, of the microdevice 2010, and at least one contact 2014 for the micro device is on asecond side, e.g. opposite or bottom, different from the first side ofmicro device 2010.

The dielectric layers 2018 and 2020 in the different embodiments may bea stack of different layers or a single layer. In one embodiment, a thinALD (atomic layer deposition) dielectric layer may be used first andthen a PECVD deposited dielectric, e.g. SiN, layer or layers may be usedto ensure better coverage for avoiding shorts at the edges and cornersof the contact and electrode layers.

The biasing of the micro device 2010 may be developed by bandengineering. Using different layers with different band structure maycreate an intrinsic potential that may bias the edge (side walls or topand bottom surface) of the micro devices 2010. Other biasing andintegration methods presented here for the MIS structure 2016 may beused with the micro device structure 2010 with contact to the electrode2012 or 2014 at the same level or in the same plane.

The following embodiments, illustrated in FIGS. 27 to 30, include arraysof optoelectronic devices, in which the pixelation may be developed bycreating islands of the ohmic contact layer(s) and bonding an array ofseparated pads to the ohmic contact layer. The islands may be smallerthan the pads. Some of the semiconductor layers after the ohmic layermay be patterned. In some embodiments, the patterning of thesemiconductor layers follows the same pattern as the islands of theohmic layer.

With reference to FIG. 27(a), different conductive and active layers2022 are deposited on top of a device substrate 2020, followed by otherconductive or blocking layers 2024. The first conductive layer 2024 maybe p-type, n-type or intrinsic. To create pixelated devices, theconductivity of the first conductive layer(s) 2024 may modulated intoislands of higher performance electrical connectivity. The islands maybe smaller than, e.g. ½ to 1/10, the pixel size, e.g. pad 2032, orsmaller, whereby at least 1 to 10, preferably 2 to 8, and morepreferably more than 4, islands contact each contact pad 2032. In oneembodiment, the islands are between 1 nm to 100 nm cubes. In oneapproach, the first conductive layer(s) 2024 or part of the firstconductive layer(s) may be patterned, e.g. through lithography, stampingand other methods. In another embodiment, a very thin island layer 2026is deposited on the first conductive layer 2024, and then ideallyannealed. The annealing process may be thermal or optical or acombination thereof. The annealing may be done in ambient condition,vacuum, or different gas. In one embodiment, the island layer 2026 maycomprise ITO, gold, silver, ZnO, Ni, or other materials. The islandlayer 2026 may be deposited by various means, such as e-beam, thermal,sputtering, etc. After creation of the island 2026-i, an pad substrate2030, which includes pads 2032, and may include driving circuitry isbonded to the surface with the islands 2026-i. The bonding may bethermal compression, thermal/optical curing adhesive, eutectic, etc. Inone embodiment, the first conductive layer 2024 may comprise variedmaterials. In an embodiment, part of the first conductive layer 2024 maybe deposited to include the island layer 2026, and another part is partof the bonding pads 2032. For example, in the case of GaN LEDs the pohmic contact is comprised of Ni and Au. In one case, layer 2026 mayinclude both Ni and Au. In another case, the layer 2026 comprises onlyNi, and the pads 2032, e.g. include a Au layer at the interface. Afterthe bonding, the pressure and heat applied to the samples will assist indiffusing them into separate layers and create an improved ohmiccontact.

Between the pads 2032 may be filled with diverse types of filler toenhance the reliability of the bonding process. The filler may includematerials such as polyamide, thermally/optically annealed adhesives,etc.

Subsequently, the device substrate 2020 may be removed, and a secondcontact layer of the device layer 2022 may be exposed. The secondcontact layer may then undergo any of the aforementioned process steps,e.g. FIGS. 8 to 10, to provide top contacts, e.g. an array of topcontact pads and/or a common electrode. Alternatively, the devicesubstrate 2020 is utilized as the common electrode.

FIG. 28 illustrates a micro device structure in which differentconductive and active layers 2022 are deposited on top of the substrate2020 followed by other conductive or blocking layers 2024. The firstconductive layer 2024 may be p-type, n-type or intrinsic. To createpixelated devices, the conductivity of the first conductive layer(s)2024 are modulated, e.g. formed, into separate islands of higherperformance electrical connectivity. The islands may be smaller than,e.g. ½ to 1/10, the pixel size, e.g. pad 2032, or smaller, whereby atleast 1 to 10, preferably 2 to 8, and more preferably more than 4,islands contact each contact pad 2032. In a preferred embodiment, theislands are between 1 nm to 100 nm tall and wide. In one embodiment, thefirst conductive layer 2024 or part of the first conductive layer 2024may be patterned, e.g. through lithography, stamping and other methods.In another embodiment, a very thin island layer 2026 may deposited ontop of the first conductive layer 2024 and annealed. The annealingprocess may be thermal or optical or combination thereof. The annealingmay be done in ambient condition, vacuum, or different gas. In oneembodiment, the island layer 2026 may be comprised of any one or more ofITO, gold, silver, ZnO, Ni, or other metallic or conductive materials.The island layer 2026 may be deposited by different means, such ase-beam, thermal, sputtering, etc. In addition to the formation ofislands 2026-i, the top conductive layer 2024 may also be separated,e.g. etched, into a distinct set of conductive layer islands 2024-i. Theislands 2026-i may act as a hard mask or a new mask may be used foretching the top conductive layer 2024 and forming the conductive layerislands 2024-i. For example, in the case of GaN, the islands 2026-i maybe comprised of Ni, which is a natural hard mask for etching the firstconductive, e.g. p-GaN, layer 2024, forming conductive layer islands2024-i e.g. using an inductively coupled plasma (ICP) etcher. The firstconductive layer(s) 2024 may be etched partially or fully. For example,the top conductive layer(s) 2024 may include both a p-layer and ablocking layer. In which case, the p-layer may be etched and theblocking layer may be left alone.

After creation of the islands 2026-i, the substrate 2030 which includespads 2032, and may include driving circuitry, is bonded to the surfacewith the islands 2026-I, see FIG. 28(d). The bonding can be thermalcompression, thermal/optical curing adhesive, eutectic, etc. In oneembodiment, the first conductive layer 2024 may contain variedmaterials. In this case, part of the first conductive layer 2024 may bedeposited as the island layer 2026 and another part may be part of thebonding pads 2032. For example, in case of GaN LEDs, the island layer2026, e.g. p ohmic contact, may be comprised of one or more of Ni andAu. In one embodiment, the island layer 2026 may comprise both Ni andAu. In another embodiment, the island layer 2026 may comprise only Ni,and the pads 2032 include a Au layer at the interface. After thebonding, the pressure and heat applied to the samples will assist indiffusing the separate layers and create an improved ohmic contact.

Subsequently, the device substrate 2020 may be removed, and a secondcontact layer of the device layer 2022 may be exposed. The secondcontact layer may then undergo any of the aforementioned process steps,e.g. FIGS. 8 to 10, to provide top contacts, e.g. an array of topcontact pads and/or a common electrode. Alternatively, the devicesubstrate 2020 is utilized as the common electrode.

With reference to FIG. 29, an alternative method includes all of theaforementioned steps from FIGS. 27 and 28, an further includes an extrapassivation layer 2028 deposited either between the islands 2024-i, onsidewall of the islands 2024-i or on top of the islands 2024-i. Thepassivation layer 2028 may comprise an ALD, e.g. dielectric, layer, aPECVD, e.g. dielectric, layer or a polymer. The area between the pads2032 may be filled with different fillers to enhance the reliability ofthe bonding process. The fillers may be comprised of a variety ofdifferent materials, such as polyamide, thermally/optically annealedadhesives, etc.

Subsequently, the device substrate 2020 may be removed, and a secondcontact layer of the device layers 2022 may be exposed. The secondcontact layer may then undergo any of the aforementioned process steps,e.g. FIGS. 8 to 10, to provide top contacts, e.g. an array of topcontact pads and/or a common electrode. Alternatively, the devicesubstrate 2020 is utilized as the common electrode.

FIG. 30 illustrates an embodiment in which an extra structure (layers)2029 may be developed between the first conductive layer (s) 2024 andthe active layers of the device layers 2022. The passivation layer 2028may also deposited after the device layers 2022. The passivation layer2028 may passivate some of the defects 2029A, such as trailingdislocation. Then the passivation layer 2028 either may be patterned(FIG. 30a ) or may be removed from the surface (FIG. 30b ). The firstconductive layer (s) 2024 may be deposited after. The passivation layer2028 may be comprised of an ALD, PECVD, organic or polymer layer. Inanother embodiment, a different plasma treatment, such as nitrogen,oxygen, or hydrogen plasma, may be used to create surface passivation.

While the present disclosure is susceptible to various modifications andalternative forms, specific embodiments or implementations have beenshown by way of example in the drawings and are described in detailherein. It should be understood, however, that the disclosure is notintended to be limited to the particular forms disclosed. Rather, thedisclosure is to cover all modifications, equivalents, and alternativesfalling within the spirit and scope of an invention as defined by theappended claims.

1. An optoelectronic device, including an array of micro devices, theoptoelectronic device comprising: a backplane comprising a drivingcircuit which controls the current flowing into the micro devices, andan array of pads connected to the driving circuit; an array of bottomcontacts electrically connected to the pads of the driving circuit; adevice layer structure including a monolithic active layer; at least onetop contact for the array of micro devices; and a common top electrodeconnected to all of the top contacts.
 2. The device according to claim1, wherein the at least one top contact comprises an array of topcontacts corresponding to the bottom contacts.
 3. The device accordingto claim 1, wherein the device layer structure includes a top conductivelayer, a bottom conductive layer, and the monolithic active layertherebetween.
 4. The device according to claim 3, wherein the array oftop contacts comprises an array of top conductive layer sectionscorresponding to the array of top contacts extending from the topconductive layer.
 5. The device according to claim 4, wherein the arrayof top contacts includes a barrier between each top contact
 6. Thedevice according to claim 5, further comprising an array of colourconversion elements on top of the common top electrode, corresponding tothe array of top contacts with a bank structure between each colourconversion element.
 7. The device according to claim 6, wherein the bankstructure and the barrier comprise a same combined bank structure; andwherein the common top electrode includes recesses for receiving thecombined bank structures.
 8. The device according to claim 3, whereinthe array of top contacts includes a barrier between each top contact;and wherein each barrier comprises an array of top conductive layersections extending from the top conductive layer; and further comprisinga dielectric layer between the top conductive layer sections and thecommon top electrode.
 9. The device according to claim 8, furthercomprising an array of colour conversion elements, corresponding to thearray of top contacts between the array of top conductive layersections.
 10. The device according to claim 9, wherein the common topelectrode includes an array of raised sections corresponding to thearray of bottom contacts and extending between the top conductive layersections.
 11. The device according to claim 10, further comprisingcolour conversion elements between each of the raised sections and thetop conductive layer.
 12. The device according to claim 3, furthercomprising a dielectric material between each of the bottom contacts.13. The device according to claim 12, wherein the dielectric materialextends into recesses in the bottom conductive layer between raisedsections extending from the bottom conductive layer in an arraycorresponding to the bottom contacts.
 14. The device according to claim3, wherein the array of bottom contacts includes an array of raisedsections in the bottom conductive layer corresponding to the array ofbottom contacts.
 15. The device according to claim 14, wherein the arrayof raised sections includes an array of island contacts, each less than½ a size of one of the pads, whereby a plurality of island contactscontact each pad.
 16. The device according to claim 3, wherein the arrayof bottom contacts includes an array of island contacts between the padsand the bottom conductive layer, each island contact less than ½ a sizeof one of the pads, whereby a plurality of island contacts contact eachpad.
 17. A method of fabricating an optoelectronic device, including anarray of micro devices, comprising: forming a device layer structure,including a monolithic active layer, on a substrate; forming an array offirst contacts on the device layer structure defining the array of microdevices; mounting the array of first contacts to a backplane comprisinga driving circuit which controls the current flowing into the array ofmicro devices, and an array of pads connected to the driving circuit;removing the substrate; and forming a second contact layer.
 18. Themethod according to claim 17, wherein forming the second contact layercomprises forming an array of second contacts corresponding to the arrayof first contacts.
 19. The method according to claim 18, wherein thestep of forming the device layer structure includes: forming a secondconductive layer on the substrate, forming the monolithic active layeron the first conductive layer; and forming a first conductive layer onthe active layer.
 20. The method according to claim 19, wherein the stepof forming the array of second contacts comprises forming an array ofsecond conductive layer sections extending from the second conductivelayer.
 21. The method according to claim 20, wherein the step of formingthe array of second conductive layer sections comprising etching thesecond conductive layer to form the array of second conductive layersections.
 22. The method according to claim 20, wherein the step offorming the array of second conductive layer sections comprising laserablating the second conductive layer to form the array of secondconductive layer sections.
 23. The method according to claim 20, whereinthe step of forming the array of second conductive layer sectionscomprising doping sections of the second conductive layer to form thearray of second conductive layer sections.
 24. The method according toclaim 18, wherein forming the array of second contacts includes forminga barrier between each second contact
 25. The method according to claim24, further comprising: forming a common electrode on top of the secondarray of contacts; and forming an array of colour conversion elements ontop of the common electrode, corresponding to the second array ofcontacts with a bank structure between each colour conversion element.26. The method according to claim 25, wherein forming the bank structureand the barrier comprise forming a same combined bank structure; andwherein the common top electrode includes recesses for receiving thecombined bank structures.
 27. The method according to claim 24, whereinforming the barrier comprises forming an array of second conductivelayer sections extending from the second conductive layer; and furthercomprising: forming a common top electrode in contact with the array ofsecond contacts; and forming a dielectric layer between the secondconductive layer sections and the common top electrode.
 28. The methodaccording to claim 27, further comprising forming an array of colourconversion elements, corresponding to the array of second contactsbetween the array of second conductive layer sections.
 29. The methodaccording to claim 27, wherein forming the common top electrode includesforming an array of raised sections corresponding to the array of secondcontacts and extending between the second conductive layer sections. 30.The method according to claim 29, further comprising depositing colourconversion elements between each of the raised sections and the secondconductive layer.
 31. The method according to claim 19, furthercomprising depositing a dielectric material between each first contact.32. The method according to claim 31, further comprising formingrecessing in the first conductive layer into which the dielectricmaterial extends.
 33. The method according to claim 19, wherein the stepof forming the array of first contacts comprises forming an array offirst conductive layer sections extending from the first conductivelayer.
 34. The method according to claim 33, wherein the step of formingthe array of first conductive layer sections comprising etching thefirst conductive layer to form the array of first conductive layersections.
 35. The method according to claim 33, wherein the step offorming the array of first conductive layer sections comprising laserablating the first conductive layer to form the array of firstconductive layer sections.
 36. The method according to claim 33, whereinthe step of forming the array of first conductive layer sectionscomprising doping sections of the first conductive layer to form thearray of first conductive layer sections.
 37. The method according toclaim 33, wherein forming the array of first conductive layer sectionsincludes forming an array of island contacts, each less than ½ a size ofone of the pads, whereby a plurality of island contacts contact eachpad.
 38. The method according to claim 19, wherein forming the array offirst contacts includes forming an array of island contacts on the firstconductive layer, each island contact less than ½ a size of one of thepads, whereby a plurality of island contacts contact each pad.
 39. Themethod according to claim 38, wherein the step of forming the array offirst contacts further comprises forming an array of first conductivelayer sections extending from the first conductive layer.
 40. The methodaccording to claim 39, wherein each of the first conductive layersections comprises a width substantially the same as each islandcontact.